UM10462
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© NXP B.V. 2016. All rights reserved.
User manual
Rev. 5.5 — 21 December 2016
54 of 523
NXP Semiconductors
UM10462
Chapter 3: LPC11U3x/2x/1x System control block
optionally two additional phases. The CCO frequency range is 156 MHz to
320 MHz.These clocks are either divided by 2
P by the programmable post divider to
create the output clocks, or are sent directly to the outputs. The main output clock is then
divided by M by the programmable feedback divider to generate the feedback clock. The
output signal of the phase-frequency detector is also monitored by the lock detector, to
signal when the PLL has locked on to the input clock.
3.10.1 Lock detector
The lock detector measures the phase difference between the rising edges of the input
and feedback clocks. Only when this difference is smaller than the so called “lock
criterion” for more than eight consecutive input clock periods, the lock output switches
from low to high. A single too large phase difference immediately resets the counter and
causes the lock signal to drop (if it was high). Requiring eight phase measurements in a
row to be below a certain figure ensures that the lock detector will not indicate lock until
both the phase and frequency of the input and feedback clocks are very well aligned. This
effectively prevents false lock indications, and thus ensures a glitch free lock signal.
3.10.2 Power-down control
To reduce the power consumption when the PLL clock is not needed, a Power-down
mode has been incorporated. This mode is enabled by setting the SYSPLL_PD bit to one
in the Power-down configuration register (
). In this mode, the internal current
reference will be turned off, the oscillator and the phase-frequency detector will be
stopped and the dividers will enter a reset state. While in Power-down mode, the lock
output will be low to indicate that the PLL is not in lock. When the Power-down mode is
terminated by setting the SYSPLL_PD bit to zero, the PLL will resume its normal
operation and will make the lock signal high once it has regained lock on the input clock.
3.10.3 Divider ratio programming
Post divider
The division ratio of the post divider is controlled by the PSEL bits. The division ratio is two
times the value of P selected by PSEL bits as shown in
and
guarantees an output clock with a 50% duty cycle.
Feedback divider
The feedback divider’s division ratio is controlled by the MSEL bits. The division ratio
between the PLL’s output clock and the input clock is the decimal value on MSEL bits plus
one, as specified in
Changing the divider values
Changing the divider ratio while the PLL is running is not recommended. As there is no
way to synchronize the change of the MSEL and PSEL values with the dividers, the risk
exists that the counter will read in an undefined value, which could lead to unwanted
spikes or drops in the frequency of the output clock. The recommended way of changing
between divider settings is to power down the PLL, adjust the divider settings and then let
the PLL start up again.
