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UM10462

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User manual

Rev. 5.5 — 21 December 2016

347 of 523

NXP Semiconductors

UM10462

Chapter 15: LPC11U3x/2x/1x 16-bit counter/timers CT16B0/1

15.7.12 PWM Control register

The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).

For each timer, a maximum of three single edge controlled PWM outputs can be selected
on the CT16Bn_MAT[1:0] outputs. One additional match register determines the PWM
cycle length. When a match occurs in any of the other match registers, the PWM output is
set to HIGH. The timer is reset by the match register that is configured to set the PWM
cycle length. When the timer is reset to zero, all currently HIGH match outputs configured
as PWM outputs are cleared.

7:5

SELCC

When bit 4 is a 1, these bits select which capture input edge
will cause the timer and prescaler to be cleared. These bits
have no effect when bit 4 is low. Values 0x6 to 0x7 are
reserved.

0

0x0

Rising Edge of CT16B1_CAP0 clears the timer (if bit 4 is
set).

0x1

Falling Edge of CT16B1_CAP0 clears the timer (if bit 4 is
set).

0x2

Rising Edge of CT16B1_CAP1 clears the timer (if bit 4 is
set).

0x3

Falling Edge of CT16B1_CAP1 clears the timer (if bit 4 is
set).

0x4

Reserved.

0x5

Reserved.

31:8

-

-

Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.

-

Table 313. Count Control Register (CTCR, address 0x4001 0070 (CT16B1)) bit description

Bit

Symbol

Value

Description

Reset
value

Table 314. PWM Control Register (PWMC, address 0x4000 C074 (CT16B0) and 0x4001 0074

(CT16B1)) bit description

Bit

Symbol

Value

Description

Reset
value

0

PWMEN0

PWM mode enable for channel0.

0

0

CT16Bn_MAT0 is controlled by EM0.

1

PWM mode is enabled for CT16Bn_MAT0.

1

PWMEN1

PWM mode enable for channel1.

0

0

CT16Bn_MAT01 is controlled by EM1.

1

PWM mode is enabled for CT16Bn_MAT1.

2

PWMEN2

PWM mode enable for channel2.

0

0

CT16Bn_MAT2 is controlled by EM2.

1

PWM mode is enabled for CT16Bn_MAT2.

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Summary of Contents for LPC11U1x

Page 1: ...016 User manual Document information Info Content Keywords LPC11U3x 2x 1x ARM Cortex M0 microcontroller LPC11U12 LPC11U14 LPC11U13 USB LPC11U22 LPC11U23 LPC11U24 LPC11U34 LPC11U35 LPC11U36 LPC11U37 LP...

Page 2: ...event Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK 0 On success2 ERR_USBD_INVALID_REQ 0x00040001 Invalid event type Added on chip local RAM to Sectio...

Page 3: ...dated In deep power down mode this pin must be pulled HIGH externally The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed See Chapter 8 LPC11U3x...

Page 4: ...c OS Remove the following step to execute before entering Deep power down Enable the IRC This step is not longer required See Section 3 9 6 Deep power down mode Register offset of the CR1 register cor...

Page 5: ...f the BYPASS bit corrected in Table 13 System oscillator control register SYSOSCCTRL address 0x4004 8020 bit description Description of USB CDC device class updated in Table 186 USBD_CDC_API class str...

Page 6: ...I O Handler is a software library supported hardware engine that can be used to add performance connectivity and flexibility to system designs It is available on the LPC11U37HFBD64 401 The I O Handle...

Page 7: ...modules enables an interrupt based on a programmable pattern of input states of a group of GPIO pins High current source output driver 20 mA on one pin P0_7 High current sink driver 20 mA on true open...

Page 8: ...wer Management Unit to minimize power consumption during Sleep Deep sleep Power down and Deep power down modes Power On Reset POR Brownout detect with four separate thresholds for interrupt and forced...

Page 9: ...ckage 48 leads body 7 7 1 4 mm SOT313 2 LPC11U35FHN33 401 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals body 7 7 0 85 mm n a LPC11U35FBD48 401 LQFP48 plastic low p...

Page 10: ...1 1 2 8 54 LPC11U34FHN33 311 40 8 8 4 1 1 2 8 26 LPC11U34FBD48 311 40 8 8 4 1 1 2 8 40 LPC11U34FHN33 421 48 8 2 10 4 1 1 2 8 26 LPC11U34FBD48 421 48 8 2 10 4 1 1 2 8 40 LPC11U35FHN33 401 64 8 2 10 4...

Page 11: ...2 13 14 slave slave slave slave ROM 16 kB slave AHB LITE BUS GPIO ports 0 1 CLKOUT IRC WDO SYSTEM OSCILLATOR POR PLL0 USB PLL BOD 10 bit ADC USART SMARTCARD INTERFACE AD 7 0 RXD TXD CTS RTS DTR SCLK G...

Page 12: ...SYSTEM FUNCTIONS RESET SWD JTAG LPC11U2x slave slave slave slave ROM 16 kB slave AHB LITE BUS GPIO ports 0 1 CLKOUT IRC WDO SYSTEM OSCILLATOR POR PLL0 USB PLL BOD 10 bit ADC USART SMARTCARD INTERFACE...

Page 13: ...TROL SYSTEM FUNCTIONS RESET SWD JTAG LPC11U3x slave slave master slave slave ROM 16 kB slave AHB LITE BUS GPIO ports 0 1 I O HANDLER 3 IOH_ 20 0 CLKOUT IRC WDO SYSTEM OSCILLATOR POR PLL0 USB PLL BOD 1...

Page 14: ...32 4 2 n a Figure 4 LPC11U14FET48 201 32 4 2 n a Figure 4 LPC11U22FBD48 301 16 6 2 1 kB Figure 5 LPC11U23FBD48 301 24 6 2 1 kB Figure 5 LPC11U24FHI33 301 32 6 2 2 kB Figure 5 LPC11U24FBD48 301 32 6 2...

Page 15: ...several distinct memory regions shown in the following figures Figure 4 shows the overall map of the entire address space from the user program viewpoint following reset The AHB peripheral area is 2...

Page 16: ...T SMART CARD PMU I2C bus 20 21 reserved 10 13 reserved reserved reserved 25 31 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved 0x0000 0000 0 GB 0 5 GB 4 GB 1 GB 0x1000 1000 0x1FFF 0000 0...

Page 17: ...3 reserved reserved reserved 25 31 reserved 0 1 2 3 4 5 6 7 8 9 16 15 14 17 18 reserved reserved 0x0000 0000 0 GB 0 5 GB 4 GB 1 GB 0x1000 1800 0x1FFF 0000 0x1FFF 4000 0x2000 0000 0x5000 0000 0x5000 40...

Page 18: ...0 5 GB 4 GB 1 GB 0x1000 0000 0x1FFF 0000 0x1FFF 4000 0x2000 0000 0x5000 0000 0x5000 4000 0xFFFF FFFF reserved reserved reserved 2 kB USB RAM LPC11U34 421 LPC11U35 401 501 LPC11U36 401 501 LPC11U37 401...

Page 19: ...s 3 3 Pin description Table 4 shows pins that are associated with system control block functions 3 4 Clocking and power control See Figure 7 for an overview of the LPC11U3x 2x 1x Clock Generation Unit...

Page 20: ...7 LPC11U3x 2x 1x CGU block diagram system oscillator watchdog oscillator IRC oscillator USB PLL USBPLLCLKSEL USB clock select SYSTEM CLOCK DIVIDER SYSAHBCLKCTRLn AHB clock enable CPU system control P...

Page 21: ...control 0x080 Table 15 0x02C Reserved SYSRSTSTAT R W 0x030 System reset status register 0x3 0x3 Table 16 SYSPLLCLKSEL R W 0x040 System PLL clock source select 0x1 0x1 Table 17 SYSPLLCLKUEN R W 0x044 S...

Page 22: ...Select register 2 0 0 Table 40 PINTSEL3 R W 0x184 GPIO Pin Interrupt Select register 3 0 0 Table 40 PINTSEL4 R W 0x188 GPIO Pin Interrupt Select register 4 0 0 Table 40 PINTSEL5 R W 0x18C GPIO Pin Int...

Page 23: ...The input frequency is multiplied to a higher frequency and then divided down to provide the actual clock used by the CPU peripherals and memories The PLL can produce a clock up to the maximum allowe...

Page 24: ...MHz from various clock sources The input frequency is multiplied up to a high frequency then divided down to provide the actual clock 48 MHz clock used by the USB subsystem Remark The USB PLL must be...

Page 25: ...11111 Division ratio M 32 0x000 6 5 PSEL Post divider ratio P The division ratio is 2 P 0x00 0x0 P 1 0x1 P 2 0x2 P 4 0x3 P 8 31 7 Reserved Do not write ones to reserved bits 0x00 Table 12 USB PLL stat...

Page 26: ...ted as wdt_osc_clk Fclkana 2 1 DIVSEL 9 4 kHz to 2 3 MHz nominal values Remark Any setting of the FREQSEL bits will yield a Fclkana value within 40 of the listed frequency value The watchdog oscillato...

Page 27: ...KUEN register see Section 3 5 12 must be toggled from LOW to HIGH for the update to take effect Table 15 Internal resonant crystal control register IRCCTRL address 0x4004 8028 bit description Bit Symb...

Page 28: ...ber 2016 28 of 523 NXP Semiconductors UM10462 Chapter 3 LPC11U3x 2x 1x System control block Table 17 System PLL clock source select register SYSPLLCLKSEL address 0x4004 8040 bit description Bit Symbol...

Page 29: ...d off 3 5 14 USB PLL clock source update enable register This register updates the clock source of the USB PLL with the new input clock after the USBPLLCLKSEL register has been written to In order for...

Page 30: ...write a zero to bit 0 of this register then write a one 3 5 17 System clock divider register This register controls how the main clock is divided to provide the system clock to the core memories and...

Page 31: ...ystem AHB clock divider values 0 System clock disabled 1 Divide by 1 to 255 Divide by 255 0x1 31 8 Reserved Table 24 System clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description Bit...

Page 32: ...e 12 USART Enables clock for UART 0 Disable 1 Enable 13 ADC Enables clock for ADC 0 0 Disable 1 Enable 14 USB Enables clock to the USB register interface 0 0 Disable 1 Enable 15 WWDT Enables clock for...

Page 33: ...e 1 Enable 25 Reserved 26 RAM1 Enables SRAM1 block at address 0x2000 0000 See Section 3 1 for availability of this bit 0 0 Disable 1 Enable 27 USBRAM Enables USB SRAM block at address 0x2000 4000 0 0...

Page 34: ...the clock source to the main clock ensure that the system PLL and the USB PLL are running to make both clock sources available for switching The main clock must be set to 48 MHz and configured with th...

Page 35: ...CLKOUT pin with the new clock after the CLKOUTSEL register has been written to In order for the update to take effect at the input of the CLKOUT pin first write a zero to bit 0 of this register then...

Page 36: ...reshold values for sending a BOD interrupt to the NVIC and for forced reset Reset and interrupt threshold values listed in Table 36 are typical values Table 32 CLKOUT clock source update enable regist...

Page 37: ...LEV BOD reset level 0 0x0 Level 0 The reset assertion threshold voltage is 1 46 V the reset de assertion threshold voltage is 1 63 V 0x1 Level 1 The reset assertion threshold voltage is 2 06 V the res...

Page 38: ...nterrupt source for the NMI you must first disable the NMI source by setting bit 31 in this register to 0 Then change the source by updating the IRQN bits and re enable the NMI source by setting bit 3...

Page 39: ...ck signal For details of how to use the USB need_clock signal for waking up the part from Deep sleep or Power down modes see Section 11 7 6 Table 40 Pin interrupt select registers PINTSEL0 to 7 addres...

Page 40: ...e in these registers must be enabled in the NVIC Table 59 in order to successfully wake the LPC11U3x 2x 1x from deep sleep or power down mode The STARTERP1 register enables the WWDT interrupt the BOD...

Page 41: ...e configured to remain running through this register The WDTOSC_PD value written to the PDSLEEPCFG register is overwritten if the LOCK bit in the WWDT MOD register see Table 337 is set See Section 17...

Page 42: ...ol Value Description Reset value Table 46 Wake up configuration register PDAWAKECFG address 0x4004 8234 bit description Bit Symbol Value Description Reset value 0 IRCOUT_PD IRC oscillator output wake...

Page 43: ...9 0 Reserved 0 10 USBPAD_PD USB transceiver wake up configuration 1 0 USB transceiver powered 1 USB transceiver powered down 11 Reserved Always write this bit as 1 1 12 Reserved Always write this bit...

Page 44: ...11 Reserved Always write this bit as 1 1 12 Reserved Always write this bit as 0 0 15 13 Reserved Always write these bits as 111 111 31 16 Reserved Table 47 Power configuration register PDRUNCFG addre...

Page 45: ...e Arm software reset POR BOD reset External reset and Watchdog reset the following processes are initiated 1 The IRC starts up After the IRC start up time maximum of 6 s on power up the IRC provides a...

Page 46: ...ts an interrupt signal to the NVIC or issues a reset depending on the value of the BODRSTENA bit in the BOD control register Table 36 The interrupt signal can be enabled for interrupt in the Interrupt...

Page 47: ...clock source to be on independently of the Deep sleep and Power down mode software configuration through the PDSLEEPCFG register For details see Section 17 7 If the part uses Deep sleep mode with the...

Page 48: ...RL Table 9 and the SYSAHBCLKDIV register Table 23 Selected peripherals USART SSP0 1 USB CLKOUT use individual peripheral clocks with their own clock dividers The peripheral clocks can be shut down thr...

Page 49: ...the IRC continues to clock the WWDT in Deep sleep mode Deep sleep mode eliminates all power used by analog peripherals and all dynamic power used by the processor itself memory systems and related co...

Page 50: ...Table 36 WWDT signal if the watchdog oscillator is enabled in the PDSLEEPCFG register WWDT interrupt using the interrupt wake up register 1 Table 44 The WWDT interrupt must be enabled in the NVIC The...

Page 51: ...st be performed to enter Power down mode 1 The PD bits in the PCON register must be set to 0x2 Table 54 2 Select the power configuration in Power down mode in the PDSLEEPCFG Table 45 register 3 If the...

Page 52: ...EL register after waking up 3 9 6 Deep power down mode In Deep power down mode power and clocks are shut off to the entire chip with the exception of the WAKEUP pin The Deep power down mode is control...

Page 53: ...ot a cold reset 3 Clear the deep power down flag in the PCON register Table 54 4 Optional Read the stored data in the general purpose registers Section 4 3 2 5 Set up the PMU for the next Deep power d...

Page 54: ...duce the power consumption when the PLL clock is not needed a Power down mode has been incorporated This mode is enabled by setting the SYSPLL_PD bit to one in the Power down configuration register Ta...

Page 55: ...In this mode the internal current reference will be turned off the oscillator and the phase frequency detector will be stopped and the dividers will enter a reset state While in Power down mode the l...

Page 56: ...cember 2016 User manual Table 53 Register overview PMU base address 0x4003 8000 Name Access Address offset Description Reset value Reference PCON R W 0x000 Power control register 0x0 Table 54 GPREG0 R...

Page 57: ...eep power down the hysteresis of the WAKEUP input pin has to be disabled in this register before entering Deep power down mode in order for the chip to wake up 7 4 Reserved Do not write ones to this b...

Page 58: ...agement Unit PMU 4 4 Functional description For details of entering and exiting reduced power modes see Section 3 9 10 WAKEUPHYS WAKEUP pin hysteresis enable 0x0 0 Hysteresis for WAKUP pin disabled 1...

Page 59: ...al description The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile The power configuration routine configures the LPC11U3x 2x...

Page 60: ...able 0 Ptr to Device Table n set_pll set_power Ptr to Function 2 Ptr to Function 0 Ptr to Function 1 Ptr to Function n Power API function table Device n ROM Driver Table 0x1FFF 1FF8 0x0 0x04 0x08 0x0C...

Page 61: ...set to 1 Table 21 set_pll attempts to find a PLL setup that matches the calling parameters Once a combination of a feedback divider value SYSPLLCTRL M a post divider ratio SYSPLLCTRL P and the system...

Page 62: ...ck at exactly the rate specified in Param1 If it is unlikely that an exact match can be found input parameter mode Param2 should be used to specify if the actual system clock can be less than or equal...

Page 63: ...bove code specifies a 12 MHz PLL input clock and a system clock of exactly 60 MHz The application was ready to infinitely wait for the PLL to lock But the expected system clock of 60 MHz exceeds the m...

Page 64: ...system clock is 36 MHz 5 6 1 4 6 System clock approximately equal to the expected value command 0 12000 command 1 16500 command 2 CPU_FREQ_APPROX command 3 0 rom pWRD set_pll command result The above...

Page 65: ...ons define PWR_CMD_SUCCESS 0 define PWR_INVALID_FREQ 1 define PWR_INVALID_MODE 2 Fig 12 Power profiles usage using power profiles and changing system clock current_clock new_clock new_mode use power r...

Page 66: ...e more processing capability to the application CPU performance is 30 better than the default option PWR_EFFICIENCY setting was designed to find a balance between active current and the CPU s ability...

Page 67: ...67 of 523 NXP Semiconductors UM10462 Chapter 5 LPC11U3x 2x 1x Power profiles rom pWRD set_power command result The above code specifies that an application is running at the main and system clock of 2...

Page 68: ...32 vectored interrupts 4 programmable interrupt priority levels with hardware priority level masking Software interrupt generation Support for NMI 6 4 Interrupt sources Table 59 lists the interrupt so...

Page 69: ...0 SSP0 interrupt Tx FIFO half empty Rx FIFO half full Rx Timeout Rx Overrun 21 USART USART interrupt Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out In...

Page 70: ...ending Register 0 This register allows changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions 0 Table 64 0x284 Reserved 0 IABR0 RO 0...

Page 71: ...ntains the 2 bit priority fields for interrupts 24 to 27 0 Table 72 IPR7 R W 0x41C Interrupt Priority Registers 7 This register allows assigning a priority to each interrupt This register contains the...

Page 72: ...E_BOD Interrupt enable 0 27 ISE_FLASH Interrupt enable 0 28 Reserved 0 29 Reserved 0 30 ISE_USB_WAKEKUP Interrupt enable 0 31 ISE_IOH Interrupt enable 0 Table 61 Interrupt Set Enable Register 0 regist...

Page 73: ...ble 0 23 ICE_USB_FIQ Interrupt disable 0 24 ICE_ADC0 Interrupt disable 0 25 ICE_WWDT Interrupt disable 0 26 ICE_BOD Interrupt disable 0 27 ICE_FLASH Interrupt disable 0 28 Reserved 0 29 Reserved 0 30...

Page 74: ...0 ISP_SSP0 Interrupt pending set 0 21 ISP_USART0 Interrupt pending set 0 22 ISP_USB_IRQ Interrupt pending set 0 23 ISP_USB_FIQ Interrupt pending set 0 24 ISP_ADC Interrupt pending set 0 25 ISP_WWDT In...

Page 75: ...8 ICP_CT32B0 Interrupt pending clear 0 19 ICP_CT32B1 Interrupt pending clear 0 20 ICP_SSP0 Interrupt pending clear 0 21 ICP_USART0 Interrupt pending clear 0 22 ICP_USB_IRQ Interrupt pending clear 0 23...

Page 76: ...USB_IRQ Interrupt active state 0 23 IAB_USB_FIQ Interrupt active state 0 24 IAB_ADC Interrupt active state 0 25 IAB_WWDT Interrupt active state 0 26 IAB_BOD Interrupt active state 0 27 IAB_FLASH Inter...

Page 77: ...T5 Interrupt Priority 0 highest priority 3 lowest priority 0 21 16 These bits ignore writes and read as 0 0 23 22 IP_PIN_INT6 Interrupt Priority 0 highest priority 3 lowest priority 0 29 24 These bits...

Page 78: ...22 IP_CT32B0 Interrupt Priority 0 highest priority 3 lowest priority 0 29 24 These bits ignore writes and read as 0 0 31 30 IP_CT32B1 Interrupt Priority 0 highest priority 3 lowest priority 0 Table 71...

Page 79: ...can have one of 4 priorities where 0 is the highest priority Table 73 Interrupt Priority Register 7 IPR7 address 0xE000 E41C bit description Bit Symbol Description Reset value 5 0 These bits ignore wr...

Page 80: ...esistor or bus keeper function repeater mode Open drain mode for standard I O pins Hysteresis Input inverter Glitch filter on selected pins Analog input or digital mode for pads hosting the ADC inputs...

Page 81: ...ch pin or select the repeater mode The possible on chip resistor configurations are pull up enabled pull down enabled or no pull up pull down The default value is pull up enabled The repeater mode ena...

Page 82: ...The RESET pin has a 20 ns glitch filter not configurable 7 3 6 Open drain mode A pseudo open drain mode can be supported for all digital pins Note that except for the I2C bus pins this is not a true...

Page 83: ...KEUP pin to reset the chip and wake up from Deep power down mode An external pull up resistor is required on this pin for the Deep power down mode The reset pin includes a fixed 20 ns glitch filter 7...

Page 84: ...A IOH_3 0x0000 0080 Table 81 PIO0_6 R W 0x018 I O configuration for pin PIO0_6 USB_CONNECT SCK0 IOH_4 0x0000 0090 Table 82 PIO0_7 R W 0x01C I O configuration for pin PIO0_7 CTS IOH_5 0x0000 0090 Table...

Page 85: ...Table 106 PIO1_7 R W 0x07C I O configuration for pin PIO1_7 IOH_17 0x0000 0090 Table 107 PIO1_8 R W 0x080 I O configuration for pin PIO1_8 IOH_18 0x0000 0090 Table 108 PIO1_9 R W 0x084 I O configurat...

Page 86: ...7 PIO1_28 R W 0x0D0 I O configuration for pin PIO1_28 CT32B0_CAP0 SCLK 0x0000 0090 Table 128 PIO1_29 R W 0x0D4 I O configuration for pin PIO1_29 SCK0 CT32B0_CAP1 0x0000 0090 Table 129 R W 0x0D8 Reserv...

Page 87: ...PIO0_1 address 0x4004 4004 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 000 0x0 PIO0_1 0x1 CLKOUT 0x2 CT32B0_MAT2 0x3 USB_FTOGG...

Page 88: ...nabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin r...

Page 89: ...4 400C bit description continued Bit Symbol Value Description Reset value Table 80 PIO0_4 register PIO0_4 address 0x4004 4010 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects...

Page 90: ...scription continued Bit Symbol Value Description Reset value Table 82 PIO0_6 register PIO0_6 address 0x4004 4018 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function...

Page 91: ...n resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input i...

Page 92: ...Reserved 0 Table 84 PIO0_8 register PIO0_8 address 0x4004 4020 bit description continued Bit Symbol Value Description Reset value Table 85 PIO0_9 register PIO0_9 address 0x4004 4024 bit description Bi...

Page 93: ...SWCLK_PIO0_10 address 0x4004 4028 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 000 0x0 SWCLK 0x1 PIO0_10 0x2 SCK0 0x3 CT16B0_M...

Page 94: ...4 3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeate...

Page 95: ...4 3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeate...

Page 96: ...3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater...

Page 97: ...T1 4 3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repea...

Page 98: ...MAT2 4 3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Rep...

Page 99: ...ed 000 0x0 PIO0_16 0x1 AD5 0x2 CT32B1_MAT3 0x3 IOH_8 4 3 MODE Selects function mode on chip pull up pull down resistor control 10 0x0 Inactive no pull down pull up resistor enabled 0x1 Pull down resis...

Page 100: ...p resistor enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1...

Page 101: ...de 31 11 Reserved 0 Table 94 PIO0_18 register PIO0_18 address 0x4004 4048 bit description continued Bit Symbol Value Description Reset value Table 95 PIO0_19 register PIO0_19 address 0x4004 404C bit d...

Page 102: ...register PIO0_20 address 0x4004 4050 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 000 0x0 PIO0_20 0x1 CT16B1_CAP0 4 3 MODE Sele...

Page 103: ...x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as...

Page 104: ...ut glitch filter 0 0 Filter enabled 1 Filter disabled 9 Reserved 0 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled Remark This is not a true open drain mode 31 11 Reserved 0 Table 98 PIO0_...

Page 105: ...ain mode enabled Remark This is not a true open drain mode 31 11 Reserved 0 Table 99 PIO0_23 register PIO0_23 address 0x4004 405C bit description continued Bit Symbol Value Description Reset value Tab...

Page 106: ...PIO1_1 address 0x4004 4064 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 0 0x0 PIO1_1 0x1 CT32B1_MAT1 0x2 IOH_11 4 3 MODE Select...

Page 107: ...sistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inver...

Page 108: ...up above VDD 31 11 RESERVED Reserved 0 Table 103 PIO1_3 PIO1_3 address 0x4004406C bit description continued Bit Symbol Value Description Reset value Table 104 I O configuration PIO1_4 PIO1_4 address 0...

Page 109: ...e Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 000 0x0 PIO1_5 0x1 CT32B1_CAP1 0x2 IOH_15 4 3 MODE Selects function mode on chip pull up pull down resistor contr...

Page 110: ...d 001 10 OD Open drain mode 0 0 Disable 1 Open drain mode enabled This is not a true open drain mode Input cannot be pulled up above VDD 31 11 RESERVED Reserved 0 Table 106 PIO1_6 register PIO1_6 addr...

Page 111: ...108 PIO1_8 register PIO1_8 address 0x4004 4080 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x2 to 0x7 are reserved 0 0x0 PIO1_8 0x1 IOH_18 4 3 MODE S...

Page 112: ...p resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin reads as...

Page 113: ...4 4088 bit description continued Bit Symbol Value Description Reset value Table 111 PIO1_11 register PIO1_11 address 0x4004 408C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selec...

Page 114: ...ull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inverted HIGH on pin read...

Page 115: ...11 Reserved 0 Table 113 PIO1_13 register PIO1_13 address 0x4004 4094 bit description continued Bit Symbol Value Description Reset value Table 114 PIO1_14 register PIO1_14 address 0x4004 4098 bit desc...

Page 116: ...r PIO1_15 address 0x4004 409C bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x4 to 0x7 are reserved 000 0x0 PIO1_15 0x1 DCD 0x2 CT16B0_MAT2 0x3 SCK1 4 3...

Page 117: ...ed 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads...

Page 118: ...p above VDD 31 11 RESERVED Reserved 0 Table 117 PIO1_17 register PIO1_17 address 0x4004 40A4 bit description continued Bit Symbol Value Description Reset value Table 118 PIO1_18 register PIO1_18 addre...

Page 119: ...set value Table 119 PIO1_19 register PIO1_19 address 0x4004 40AC bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 000 0x0 PIO1_19 0...

Page 120: ...ed 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads...

Page 121: ...mode 31 11 Reserved 0 Table 121 PIO1_21 register PIO1_21 address 0x4004 40B4 bit description continued Bit Symbol Value Description Reset value Table 122 PIO1_22 register PIO1_22 address 0x4004 40B8 b...

Page 122: ...ster PIO1_23 address 0x4004 40BC bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x3 to 0x7 are reserved 000 0x0 PIO1_23 0x1 CT16B1_MAT1 0x2 SSEL1 4 3 MOD...

Page 123: ...sistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin reads as 0 1 Input inver...

Page 124: ...ption continued Bit Symbol Value Description Reset value Table 126 PIO1_26 register PIO1_26 address 0x4004 40C8 bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function V...

Page 125: ...enabled 0x1 Pull down resistor enabled 0x2 Pull up resistor enabled 0x3 Repeater mode 5 HYS Hysteresis 0 0 Disable 1 Enable 6 INV Invert input 0 0 Input not inverted HIGH on pin reads as 1 LOW on pin...

Page 126: ...31 11 Reserved 0 Table 128 PIO1_28 register PIO1_28 address 0x4004 40D0 bit description continued Bit Symbol Value Description Reset value Table 129 PIO1_29 register PIO1_29 address 0x4004 40D4 bit d...

Page 127: ...PIO1_31 register PIO1_31 address 0x4004 40DC bit description Bit Symbol Value Description Reset value 2 0 FUNC Selects pin function Values 0x1 to 0x7 are reserved 000 0x0 PIO1_31 4 3 MODE Selects fun...

Page 128: ...2 Chapter 8 LPC11U3x 2x 1x Pin configuration Rev 5 5 21 December 2016 User manual Table 131 LPC11U3x 2x 1x pin configurations Part Package Pin configuration Pin description LPC11U1x HVQFN33 Figure 15...

Page 129: ...PIO0_22 AD6 CT16B1_MAT1 MISO1 XTALIN TDI PIO0_11 AD0 CT32B0_MAT3 PIO0_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE TMS PIO0_12 AD1 CT32B1_CAP0 RESET PIO0_0 TDO PIO0_13 AD2 CT32B1_MAT0 PIO1_19 DTR SSEL1 TRST PIO0_...

Page 130: ...CLK PIO0_10 SCK0 CT16B0_MAT2 PIO0_20 CT16B1_CAP0 PIO0_9 MOSI0 CT16B0_MAT1 PIO0_2 SSEL0 CT16B0_CAP0 PIO0_8 MISO0 CT16B0_MAT0 PIO1_26 CT32B0_MAT2 RXD PIO1_21 DCD MISO1 PIO1_27 CT32B0_MAT3 TXD PIO1_31 PI...

Page 131: ...13 PIO1_19 TRST PIO0_14 RESET PIO0_0 TDO PIO0_13 PIO0_1 TMS PIO0_12 PIO1_7 PIO1_11 VSS TDI PIO0_11 XTALIN PIO1_29 XTALOUT PIO0_22 VDD PIO1_8 PIO0_20 SWCLK PIO0_10 PIO1_10 PIO0_9 PIO0_2 PIO0_8 PIO1_26...

Page 132: ...External reset input with 20 ns glitch filter A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor executi...

Page 133: ...O SCK0 Serial clock for SSP0 PIO0_7 CTS 16 23 G7 5 I PU I O PIO0_7 General purpose digital input output pin high current output driver I CTS Clear To Send input for USART PIO0_8 MISO0 CT16B0_MAT0 17...

Page 134: ...ch output 1 for 32 bit timer 1 SWDIO PIO0_15 AD4 CT32B1_MAT2 25 39 B6 6 I PU I O SWDIO Serial wire debug input output I O PIO0_15 General purpose digital input output pin I AD4 A D converter input 4 O...

Page 135: ...1 CT16B1_MAT0 MOSI1 12 17 G4 3 I PU I O PIO0_21 General purpose digital input output pin O CT16B1_MAT0 Match output 0 for 16 bit timer 1 I O MOSI1 Master Out Slave In for SSP1 PIO0_22 AD6 CT16B1_MAT1...

Page 136: ...USART I CT16B0_CAP0 Capture input 0 for 16 bit timer 0 PIO1_19 DTR SSEL1 1 2 B1 3 I PU I O PIO1_19 General purpose digital input output pin O DTR Data Terminal Ready output for USART I O SSEL1 Slave...

Page 137: ...ter output for USART PIO1_28 CT32B0_CAP0 SCLK 24 H7 3 I PU I O PIO1_28 General purpose digital input output pin I CT32B0_CAP0 Capture input 0 for 32 bit timer 0 I O SCLK Serial clock input output for...

Page 138: ...s a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant includes digital input glitch filter 7 Pad provides USB functions It is designed in accordance with the USB specifi...

Page 139: ...7 PIO1_28 CT32B0_CAP1 I no PIO1_29 CT32B0_MAT0 O no PIO0_18 PIO1_24 CT32B0_MAT1 O no PIO0_19 PIO1_25 CT32B0_MAT2 O no PIO0_1 PIO1_26 CT32B0_MAT3 O no PIO0_11 PIO1_27 CT32B1 CT32B1_CAP0 I no PIO0_12 CT...

Page 140: ...function is not needed and Deep power down mode is not used I O PIO0_0 General purpose digital input output pin PIO0_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE 3 4 5 3 I PU I O PIO0_1 General purpose digital in...

Page 141: ...10 General purpose digital input output pin O SCK0 Serial clock for SSP0 O CT16B0_MAT2 Match output 2 for 16 bit timer 0 TDI PIO0_11 AD0 CT32B0_MAT3 21 32 42 6 I PU I TDI Test Data In for JTAG interfa...

Page 142: ...put pin O TXD Transmitter output for USART Used in UART ISP mode O CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIO0_20 CT16B1_CAP0 7 9 11 3 I PU I O PIO0_20 General purpose digital input output pin...

Page 143: ...output for USART PIO1_14 DSR CT16B0_MAT1 RXD 37 49 3 I PU I O PIO1_14 General purpose digital input output pin I DSR Data Set Ready input for USART O CT16B0_MAT1 Match output 1 for 16 bit timer 0 I RX...

Page 144: ...put output pin O CT32B0_MAT2 Match output 2 for 32 bit timer 0 I RXD Receiver input for USART PIO1_27 CT32B0_MAT3 TXD 12 15 3 I PU I O PIO1_27 General purpose digital input output pin O CT32B0_MAT3 Ma...

Page 145: ...input glitch filter 7 Pad provides USB functions It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only This pad is not 5 V tolerant 8 When the system...

Page 146: ...output pin open drain I O SDA I2C bus data input output open drain High current sink only if I2C Fast mode Plus is selected in the I O configuration register I O IOH_3 I O Handler input output 3 LPC11...

Page 147: ...in I AD0 A D converter input 0 O CT32B0_MAT3 Match output 3 for 32 bit timer 0 TMS PIO0_12 AD1 CT32B1_CAP0 22 C7 33 44 6 I PU I TMS Test Mode Select for JTAG interface I O PIO_12 General purpose digit...

Page 148: ...mer 0 I O SCLK Serial clock input output for USART in synchronous mode PIO0_18 RXD CT32B0_MAT0 31 B3 46 61 3 I PU I O PIO0_18 General purpose digital input output pin I RXD Receiver input for USART Us...

Page 149: ...IO1_4 CT32B1_CAP0 IOH_14 16 3 I PU I O PIO1_4 General purpose digital input output pin I CT32B1_CAP0 Capture input 0 for 32 bit timer 1 I O IOH_14 I O Handler input output 14 LPC11U37HFBD64 401 only P...

Page 150: ...tput pin I CT16B0_CAP1 Capture input 1 for 16 bit timer 0 I RXD Receiver input for USART PIO1_18 CT16B1_CAP1 TXD 28 3 I PU I O PIO1_18 General purpose digital input output pin I CT16B1_CAP1 Capture in...

Page 151: ...tput pin O CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIO1_26 CT32B0_MAT2 RXD IOH_19 G2 11 14 3 I PU I O PIO1_26 General purpose digital input output pin O CT32B0_MAT2 Match output 2 for 32 bit tim...

Page 152: ...ble hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant includes digital input glitch filter 7 Pad provides USB functions...

Page 153: ...is enabled in the STARTERP1 register Table 44 For the GPIO port registers enable the clock to the GPIO port register in the SYSAHBCLKCTRL register Table 24 bit 6 9 3 Features 9 3 1 GPIO pin interrupt...

Page 154: ...t pin connected to one of the two the GPIO Grouped Interrupt blocks GROUP0 and GROUP1 the GPIO grouped interrupt registers determine which pins are enabled to generate interrupts and what the active p...

Page 155: ...ption Reset value Reference ISEL R W 0x000 Pin Interrupt Mode register 0 Table 141 IENR R W 0x004 Pin interrupt level rising edge interrupt enable register 0 Table 142 SIENR WO 0x008 Pin interrupt lev...

Page 156: ...nce B0 to B23 R W 0x0000 to 0x0018 Byte pin registers port 0 pins PIO0_0 to PIO0_23 ext 1 byte 8 bit Table 156 B32 to B63 R W 0x0020 to 0x002F Byte pin registers port 1 ext 1 byte 8 bit Table 157 W0 t...

Page 157: ...IGH or LOW for this interrupt 9 5 1 3 Pin interrupt level rising edge interrupt set register For each of the 8 pin interrupts selected in the PINTSELn registers see Table 40 one bit in the SIENR regis...

Page 158: ...ister enables the falling edge interrupt or the configures the level sensitivity depending on the pin interrupt mode configured in the ISEL register If the pin interrupt mode is edge sensitive PMODE 0...

Page 159: ...NF register depending on the pin interrupt mode configured in the ISEL register If the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is cleared If the pin interrupt mode is l...

Page 160: ...ng edge interrupt clear register CIENF address 0x4004 C018 bit description Bit Symbol Description Reset value Access 7 0 CENAF Ones written to this address clears bits in the IENF thus disabling inter...

Page 161: ...interrupt status register IST address 0x4004 C024 bit description Bit Symbol Description Reset value Access 7 0 PSTAT Pin interrupt status Bit n returns the status clears the edge interrupt or inverts...

Page 162: ...rs PORT_POL1 addresses 0x4005 C024 GROUP0 INT and 0x4006 0024 GROUP1 INT bit description Bit Symbol Description Reset value Access 31 0 POL1 Configure pin polarity of port 1 pins for group interrupt B...

Page 163: ...the pin s output bit Table 156 GPIO port 0 byte pin registers B0 to B23 addresses 0x5000 0000 to 0x5000 0018 bit description Bit Symbol Description Reset value Access 0 PBYTE Read state of the pin P0_...

Page 164: ...FFF FFFF pin is HIGH Write any value 0x0000 0001 to 0xFFFF FFFF set output bit Remark Only 0 or 0xFFFF FFFF can be read Writing any value other than 0 will set the output bit ext R W Table 160 GPIO di...

Page 165: ...tive in the P1MPORT register bit 0 P1_0 bit 1 P1_1 bit 31 P1_31 0 Read MPORT pin state write MPORT load output bit 1 Read MPORT 0 write MPORT output bit not affected 0 R W Table 164 GPIO port 0 pin re...

Page 166: ...LOW and or the corresponding bit in the MASK register is 1 write clear output bit if the corresponding bit in the MASK register is 0 1 Read pin is HIGH and the corresponding bit in the MASK register i...

Page 167: ...GPIO pin has an output bit in the GPIO block These output bits are the targets of write operations to the pins Two conditions must be met in order for a pin s output bit to be driven onto the pin 1 T...

Page 168: ...The simpler way to protect a block of code that uses a MASK register is to disable interrupts before setting the MASK register and re enable them after the last operation that uses the MPORT or MASK...

Page 169: ...37 9 6 5 Recommended practices The following lists some recommended uses for using the GPIO port registers For initial setup after Reset or re initialization write the PORT register s To change the s...

Page 170: ...he required interface needed to interface with Devices using the USB CDC ACM Class Communication Device Class function driver initialization parameter data structure Table 202 USBD_CDC_INIT_PARAM clas...

Page 171: ...07 USBD_HID_INIT_PARAM class structure HID class API functions structure This structure contains pointers to all the functions exposed by the HID function driver module Table 208 USBD_HW_API class str...

Page 172: ...device driver pointer structure Ptr to USB ROM Driver table Ptr to Device Table 2 Ptr to USB Driver Table Ptr to Device Table 1 Ptr to Device Table n hw core dfu Ptr to Function 3 Ptr to Function 1 Pt...

Page 173: ...CONTROL_MANAGEMENT_DESCRIPTOR bDescriptorType bDescriptorSubtype uint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR bDescriptorSubtype bmCapabilities uint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPT...

Page 174: ...t _CDC_LINE_CODING bDataBits Table 181 _CDC_UNION_1SLAVE_DESCRIPTOR class structure Member Description sUnion CDC_UNION_DESCRIPTORCDC_UNION_DESCRIPTOR _CDC_UNION_1SLAVE_DESCRIPTOR sUnion bSlaveInterfa...

Page 175: ...ST_PACK _HID_DESCRIPTOR _HID_DESCRIPTOR_LISTPRE_PACK struct POST_PACK _HID_DESCRIPTOR _HID_DESCRIPTOR_LIST _HID_DESCRIPTOR DescriptorList 1 1 Array of one or more descriptors Table 185 _HID_DESCRIPTOR...

Page 176: ...SC_CBW bmFlags bLUN uint8_t _MSC_CBW bLUN bCBLength uint8_t _MSC_CBW bCBLength CB uint8_t _MSC_CBW CB 16 16 Table 188 _MSC_CSW class structure Member Description dSignature uint32_t _MSC_CSW dSignatur...

Page 177: ...nter should be same as full_speed_desc device_qualifier uint8_t _USB_CORE_DESCS_T device_qualifier Pointer to USB device qualifier descriptor For full speed only implementation this pointer should be...

Page 178: ...bytes bDescriptorType uint8_t _USB_INTERFACE_DESCRIPTOR bDescriptorType INTERFACE Descriptor Type bInterfaceNumber uint8_t _USB_INTERFACE_DESCRIPTOR bInterfaceNumber Number of this interface Zero bas...

Page 179: ...tion uint8_t _USB_OTHER_SPEED_CONFIGURATION IConfiguration Index of string descriptor bmAttributes uint8_t _USB_OTHER_SPEED_CONFIGURATION bmAttributes Same as Configuration descriptor bMaxPower uint8_...

Page 180: ...TRING Descriptor Type bString uint16_t _USB_STRING_DESCRIPTOR bString UNICODE encoded string Table 198 _WB_T class structure Member Description L uint8_t _WB_T L lower byte H uint8_t _WB_T H upper byt...

Page 181: ...r Description usb_reg_base uint32_t USBD_API_INIT_PARAM usb_reg_base USB device controller s base register address mem_base uint32_t USBD_API_INIT_PARAM mem_base Base memory location from where the st...

Page 182: ...tate and back into normal operating mode Remark This event is called from USB_ISR context and hence is time critical Having delays in this callback will cause other system issues Parameters 1 hUsb Han...

Page 183: ...SBD_API_INIT_PARAM USB_Error_Event Event for error condition This event fires when USB device controller detect an error condition in the system Parameters 1 hUsb Handle to the USB device stack 2 para...

Page 184: ...g delays in this callback will prevent the device from enumerating correctly or operate properly virt_to_phys uint32_t USBD_API_INIT_PARAM virt_to_phys void vaddr Reserved parameter for future use sho...

Page 185: ...I SendNotification USBD_HANDLE_T hCdc uint8_t bNotification uint16_t data Function to send CDC class notifications to host This function is called by application layer to send CDC class notifications...

Page 186: ...his function is provided by the application software This function gets called when host sends CIC management element get requests Remark Applications implementing Abstract Control Model subclass can...

Page 187: ...pdate pBuffer pointer the stack will send STALL condition to host 2 Second when the data is received from the host This time the length param is set with number of data bytes received Parameters 1 hCd...

Page 188: ...etails Returns The call back should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to...

Page 189: ...d returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For ot...

Page 190: ...on software This function gets called when host sends a GET_ENCAPSULATED_RESPONSE request Parameters 1 hCdc Handle to CDC function driver 2 feature Communication feature type 3 buffer Pointer to a poi...

Page 191: ...rovided by the application software This function gets called when host sends a CLEAR_COMM_FEATURE request In the call back the application should Clears the settings for a particular communication fe...

Page 192: ...orCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error con...

Page 193: ...success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions CDC_InterruptEP_Hd...

Page 194: ...SBD_xxx For other error conditions Table 202 USBD_CDC_INIT_PARAM class structure Member Description Table 203 USBD_CORE_API class structure Member Description RegisterClassHandler ErrorCode_t ErrorCod...

Page 195: ...ndpoint handlers SetupStage void void USBD_CORE_API SetupStage USBD_HANDLE_T hUsb Function to set EP0 state machine in setup state This function is called by USB stack and the application layer to set...

Page 196: ...ication layer to set the EP0 state machine in status_in state This function will send zero length IN packet on EP0 to host indicating positive status Remark This interface is provided to users to invo...

Page 197: ...P0 state machine in stall state This function is called by USB stack and the application layer to generate STALL signalling on EP0 endpoint This function will also reset the EP0Data buffer Remark This...

Page 198: ...s called by application layer to initialize DFU function driver module Parameters 1 hUsb Handle to the USB device stack 2 param Structure containing DFU function driver module initialization parameter...

Page 199: ...inter is used to implement zero copy buffers See Zero Copy Data Transfer model for more details on zero copy concept 3 bwPollTimeout Pointer to a 3 byte buffer which the callback implementer should fi...

Page 200: ...ave to issue reset instead the device has to do it automatically by disconnect and connect procedure hUsbHandle DFU control structure Parameters 1 hUsb Handle DFU control structure Returns Nothing DFU...

Page 201: ...odule initialization parameters Returns Returns the required memory size in bytes init ErrorCode_t ErrorCode_t USBD_HID_API init USBD_HANDLE_T hUsb USBD_HID_INIT_PARAM_T param Function to initialize H...

Page 202: ..._INIT_PARAM report_data Pointer to an array of HID report descriptor data structure Remark This array should be of global scope HID_GetReport ErrorCode_t USBD_HID_INIT_PARAM HID_GetReport USBD_HANDLE_...

Page 203: ...cation software could provide this callback HID_GetPhysDesc handler to handle get physical descriptor requests sent by the host When host requests Physical Descriptor set 0 application should return a...

Page 204: ...ck should returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xx...

Page 205: ...andler Application which send reports to host on interrupt endpoint should provide an endpoint event handler through this data member This data member is ignored if the interface descriptor Parameters...

Page 206: ...led hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions HID_GetReportDesc ErrorCode_t USBD_HID_INIT_PARAM HID_GetReportDesc USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_...

Page 207: ...override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure Application which like the default handler should set th...

Page 208: ...and core layers On successful initialization the function returns a handle to USB device stack which should be passed to the rest of the functions Parameters 1 phUsb Pointer to the USB device stack h...

Page 209: ...to the USB device stack Returns Nothing Reset void void USBD_HW_API Reset USBD_HANDLE_T hUsb Function to Reset USB device stack and hardware controller Reset USB device stack and hardware controller...

Page 210: ...nction to set USB address assigned by host in device controller hardware This function is called automatically when USB_REQUEST_SET_ADDRESS request is received by the stack from USB host This interfac...

Page 211: ...by users who are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack Parameters 1 hUsb Handle to the USB device stack 2 pEPD Endpoint descrip...

Page 212: ...s param to 0x0 3 event Type of endpoint event See USBD_EVENT_T for more details 4 enable 1 enable event 0 disable event Returns Returns ErrorCode_t type to indicate success or error condition Return v...

Page 213: ...2 EPNum Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Returns Nothing SetTestMode ErrorCode_t ErrorCode_t USBD_HW_API SetTestMode USBD_HANDLE_T hUsb uint8_t mode...

Page 214: ...on the specified endpoint This function is called by USB stack and the application layer to queue a read request on the specified endpoint Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endp...

Page 215: ...Function to generate resume signaling on bus for remote host wake up This function is called by application layer to remotely wake up host controller when system is in suspend state Application shoul...

Page 216: ...Remark Some memory areas are not accessible by all bus masters Parameters 1 param Structure containing MSC function driver module initialization parameters Returns Returns the required memory size in...

Page 217: ...is sent in response to the SCSI Inquiry command Remark The data pointed by the pointer should be of global scope BlockCount uint32_t USBD_MSC_INIT_PARAM BlockCount Number of blocks present in the mass...

Page 218: ...ction drivers implemented in stack are written with zero copy model Meaning the stack doesn t make an extra copy of buffer before writing reading data from USB hardware FIFO Hence the parameter is poi...

Page 219: ...ata sent by the host 3 length Number of bytes to verify Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK If data in the buffer matches the data at destina...

Page 220: ...handler function address as this data member of the parameter structure Application which like the default handler should set this data member to zero before calling the USBD_MSC_API Init Remark Param...

Page 221: ...activity and remote wake up Supports SoftConnect Link Power Management LPM supported 11 4 General description The Universal Serial Bus USB is a four wire bus that supports communication between a host...

Page 222: ...analog transceiver ATX The USB ATX sends receives the bi directional USB_DP and USB_DM signals of the USB bus The SIE implements the full USB protocol layer It is completely hardwired for speed and n...

Page 223: ...can also be performed without having to unplug the cable Fig 21 USB software interface 0x00 7 0 USB EP List Start Address 8 EP_LIST ADDR OFFSET 1 0 15 NBytes CS CS Endpoint Control Status bits 31 25 A...

Page 224: ...configuration descriptor The maximum value is 500 mA A suspended device should draw a maximum of 500 A A device will go into the L2 suspend state if there is no activity on the USB bus for more than...

Page 225: ...cription The device controller can access one USB port 11 6 Register description Table 212 USB device pin description Name Direction Description VBUS I VBUS status input When this function is not enab...

Page 226: ...the HW will start responding on packets for function address DEV_ADDR 0 RW 8 SETUP SETUP token received If a SETUP token is received and acknowledged by the device this bit is set As long as this bit...

Page 227: ...erate a remote walk up Software can only write a zero to this bit when the LPM_REWP bit is set to 1 HW resets this bit when it receives a host initiated resume HW only updates the LPM_SUS bit when the...

Page 228: ...up resistor to signal a connect 0 RO 31 29 Reserved 0 RO Table 214 USB Device Command Status register DEVCMDSTAT address 0x4008 0000 bit description Bit Symbol Value Description Reset value Access Tab...

Page 229: ...Description Reset value Access 21 0 Reserved 0 R 31 22 DA_BUF Start address of the buffer pointer page where all endpoint data buffers are located 0 R W Table 218 Link Power Management register LPM ad...

Page 230: ...ve bit of the buffer indicated by the EPINUSE bit 0 R W 31 30 Reserved 0 R Table 220 USB Endpoint Buffer in use EPINUSE address 0x4008 0018 bit description Bit Symbol Description Reset value Access 1...

Page 231: ...EP1 OUT direction Software can clear this bit by writing a one to it 0 R WC 3 EP1IN Interrupt status register bit for the EP1 IN direction This bit will be set if the corresponding Active bit is clear...

Page 232: ...software If the IntOnNAK_AI is set this bit will also be set when a NAK is transmitted for the EP4 IN direction Software can clear this bit by writing a one to it 0 R WC 29 10 Reserved 0 RO 30 FRAME_...

Page 233: ...e corresponding USB interrupt status bit is set When this register is read the same value as the USB interrupt status register is returned 0 R W Table 225 USB interrupt routing register INTROUTING add...

Page 234: ...fset EP0 IN Buffer NBytes A R S TR TV Reserved Reserved R R R R R R EP1 OUT Buffer 0 Address Offset EP1 OUT Buffer 0 NBytes A D S TR RF TV EP1 OUT Buffer 1 Address Offset EP1 OUT Buffer 1 NBytes T EP1...

Page 235: ...ftware can only modify this bit when the active bit is zero S RW Stall 0 The selected endpoint is not stalled 1 The selected endpoint is stalled The Active bit has always higher priority than the Stal...

Page 236: ...RW Endpoint Type 0 Generic endpoint The endpoint is configured as a bulk or interrupt endpoint 1 Isochronous endpoint NBytes RW For OUT endpoints this is the number of bytes that can be received in th...

Page 237: ...Write EP0IN Active 1 Stall 1 0 Bytes No Write EP0OUT Active 1 Stall 1 NBytes Write DevStatus IntOnNak _CO 0 IntOnNak _CI 1 No All OUT data received Write EP0OUT Active 1 Stall 1 NBytes No No Yes Writ...

Page 238: ...nt until the NBytes value is equal to zero When NBytes goes to zero hardware clears the active bit and sets the corresponding interrupt status bit Fig 24 Flowchart of control endpoint 0 IN direction W...

Page 239: ...is a bit different between OUT and IN endpoints When data must be received for the OUT endpoint the software will set the Active bit to one and program the NBytes field to the maximum number of bytes...

Page 240: ...to 0 default to enable automatic control of the USB need_clock signal 2 Wait until USB activity is suspended by polling the DSUS bit in the DSVCMD_STAT register DSUS 1 3 The USB need_clock signal wil...

Page 241: ...manual Rev 5 5 21 December 2016 241 of 523 NXP Semiconductors UM10462 Chapter 11 LPC11U3x 2x 1x USB2 0 device controller 5 Wait until the USB leaves the suspend state by polling the DSUS bit in the DS...

Page 242: ...m to 550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator Software or hardware flow control RS 485 EIA 485 9 bit mode support with output enable RTS CT...

Page 243: ...rrupt Enable Register Contains individual interrupt enable bits for the 7 potential USART interrupts DLAB 0 0 Table 234 IIR RO 0x008 Interrupt ID Register Identifies which interrupt s are pending 0x01...

Page 244: ...SART TX FIFO The top byte is the newest character in the TX FIFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in the LCR must...

Page 245: ...Register when DLAB 1 DLL address 0x4000 8000 bit description Bit Symbol Description Reset value 7 0 DLLSB The USART Divisor Latch LSB Register along with the DLM register determines the baud rate of t...

Page 246: ...egister when DLAB 0 IER address 0x4000 8004 bit description continued Bit Symbol Value Description Reset value Table 235 USART Interrupt Identification Register Read only IIR address 0x4004 8008 bit d...

Page 247: ...terrupt is cleared upon a LSR read The USART RDA interrupt IIR 3 1 010 shares the second level priority with the CTI interrupt IIR 3 1 110 The RDA is activated when the USART Rx FIFO reaches the trigg...

Page 248: ...1 event This delay is provided to give the CPU time to write data to THR without a THRE interrupt to decode and service A THRE interrupt is set immediately if the USART THR FIFO has held two or more...

Page 249: ...l clear all bytes in USART Rx FIFO reset the pointer logic This bit is self clearing 2 TXFIFO RES TX FIFO Reset 0 0 No impact on either of USART FIFOs 1 Writing a logic 1 to FCR 2 will clear all bytes...

Page 250: ...00C bit description Bit Symbol Value Description Reset Value Table 239 USART Modem Control Register MCR address 0x4000 8010 bit description Bit Symbol Value Description Reset value 0 DTRCTRL Source fo...

Page 251: ...sertion of RTS until after it has begun sending the additional byte RTS is automatically reasserted to a low value once the receiver FIFO has reached the previous trigger level The reassertion of RTS...

Page 252: ...be set Table 240 lists the conditions for generating a Modem Status interrupt The auto CTS function typically eliminates the need for CTS interrupts When flow control is enabled a CTS state change doe...

Page 253: ...Line Status Register Read only LSR address 0x4000 8014 bit description Bit Symbol Value Description Reset Value 0 RDR Receiver Data Ready LSR 0 is set when the RBR holds an unread character and is cle...

Page 254: ...this status bit The time of break detection is dependent on FCR 0 Note The break interrupt is associated with the character at the top of the USART RBR FIFO 0 0 Break interrupt status is inactive 1 B...

Page 255: ...DSR Set upon state change of input DSR Cleared on an MSR read 0 0 No change detected on modem input DSR 1 State change detected on modem input DSR 2 TERI Trailing Edge RI Set upon low to high transit...

Page 256: ...us of auto baud pending finished Table 244 Auto baud Control Register ACR address 0x4000 8020 bit description Bit Symbol Value Description Reset value 0 START This bit is automatically cleared after a...

Page 257: ...so when auto baud is used any write to DLM and DLL registers should be done before ACR register write The minimum and the maximum baud rates supported by USART are a function of USART_PCLK and the num...

Page 258: ...ter 12 5 13 IrDA Control Register The IrDA Control Register enables and configures the IrDA mode The value of the ICR should not be changed while transmitting or receiving data or data loss or corrupt...

Page 259: ...IrDA mode enable 0 0 IrDA mode is disabled 1 IrDA mode is enabled 1 IRDAINV Serial input inverter 0 0 The serial input is not inverted 1 The serial input is inverted This has no effect on the serial o...

Page 260: ...re the standard USART baud rate divider registers and DIVADDVAL and MULVAL are USART fractional baud rate generator specific parameters The value of MULVAL and DIVADDVAL should comply to the following...

Page 261: ...1 Baud rate calculation The USART can operate with or without using the Fractional Divider In real life applications it is likely that the desired baud rate can be achieved using several different Fr...

Page 262: ...r 12 LPC11U3x 2x 1x USART Fig 28 Algorithm for setting USART dividers PCLK BR Calculating UART baudrate BR DL est PCLK 16 x BR DLest is an integer DIVADDVAL 0 MULVAL 1 True FR est 1 5 DL est Int PCLK...

Page 263: ...is 115384 This rate has a relative error of 0 16 from the originally specified 115200 12 5 15 USART Oversampling Register In most applications the USART samples received data 16 times in each nominal...

Page 264: ...vailable As soon as TxEn becomes 0 USART transmission will stop Although Table 250 describes how to use TxEn bit in order to achieve hardware flow control it is strongly suggested to let the USART har...

Page 265: ...cations Table 250 USART Transmit Enable Register TER address 0x4000 8030 bit description Bit Symbol Description Reset Value 6 0 Reserved user software should not write ones to reserved bits The value...

Page 266: ...maximum number of retransmissions that the USART will attempt if the remote device signals NACK When NACK has occurred this number of times plus one the Tx Error bit in the LSR is set an interrupt is...

Page 267: ...r direction control 1 If direction control is enabled bit DCTRL 1 pin DTR is used for direction control 4 DCTRL Auto direction control enable 0 0 Disable Auto Direction Control 1 Enable Auto Direction...

Page 268: ...s not defined NA Table 256 USART Synchronous mode control register SYNCCTRL address 0x4000 8058 bit description Bit Symbol Value Description Reset value 0 SYNC Enables synchronous mode 0 0 Disabled 1...

Page 269: ...on SYNC 1 CSRC 1 CSCEN 1 and SSDIS 1 is a difficult operating mode because SCLK applies to both directions of data flow and there is no defined mechanism to signal the receivers when valid data is pre...

Page 270: ...causes the USART to set the parity error and generate an interrupt If the receiver is disabled RS485CTRL bit 1 1 any received data bytes will be ignored and will not be stored in the RXFIFO When an a...

Page 271: ...l is enabled the selected pin will be asserted driven LOW when the CPU writes data into the TXFIFO The pin will be de asserted driven HIGH once the last bit of data has been transmitted See bits 4 and...

Page 272: ...and requirements when communicating or powering cards that use different power rails than the LPC11U3x 2x 1x 12 6 2 1 Smart card set up procedure A T 0 protocol transfer consists of 8 bits of data an...

Page 273: ...24 to enable the USART clock Thereafter software should monitor card insertion handle activation wait for answer to reset as described in ISO7816 3 12 7 Architecture The architecture of the USART is...

Page 274: ...21 December 2016 274 of 523 NXP Semiconductors UM10462 Chapter 12 LPC11U3x 2x 1x USART Fig 31 USART block diagram APB INTERFACE LCR RX DDIS LSR FCR BRG TX INTERRUPT PA 2 0 PSEL PSTB PWRITE PD 7 0 AR...

Page 275: ...Table 8 are set to 1 This de asserts the reset signal to the SSP SPI block 13 3 Features Compatible with Motorola SPI 4 wire TI SSI and National Semiconductor Microwire buses Synchronous Serial Commu...

Page 276: ...te before the start of serial data and then releases it to an inactive state after the data has been sent The active state of this signal can be high or low depending upon the selected bus and mode Wh...

Page 277: ...000 0003 Table 263 CPSR R W 0x010 Clock Prescale Register 0 Table 264 IMSC R W 0x014 Interrupt Mask Set and Clear Register 0 Table 265 RIS RO 0x018 Raw Interrupt Status Register 0x0000 0008 Table 266...

Page 278: ...bit transfer 0xC 13 bit transfer 0xD 14 bit transfer 0xE 15 bit transfer 0xF 16 bit transfer 5 4 FRF Frame Format 00 0x0 SPI 0x1 TI 0x2 Microwire 0x3 This combination is not supported and should not...

Page 279: ...riving MISO line and receiving SCLK MOSI and SSEL lines 3 SOD Slave Output Disable This bit is relevant only in slave mode MS 1 If it is 1 this blocks this SPI controller from driving the transmit dat...

Page 280: ...SP SPI Interrupt Mask Set Clear Register This register controls whether each of the four possible interrupt conditions in the SPI controller are enabled Table 263 SSP SPI Status Register SR address 0x...

Page 281: ...pt when a Receive Time out condition occurs A Receive Time out occurs when the Rx FIFO is not empty and no has not been read for a time out period The time out period is the same for master and slave...

Page 282: ...full and this interrupt is enabled 0 1 RTMIS This bit is 1 if the Rx FIFO is not empty has not been read for a time out period and this interrupt is enabled The time out period is the same for master...

Page 283: ...ch data bit into their serial shifter on the falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has bee...

Page 284: ...re 33 In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP SPI is enabled and there is valid data withi...

Page 285: ...OL 0 CPHA 1 is shown in Figure 34 which covers both single and continuous transfers In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pa...

Page 286: ...opagated on the rising edges of the SCK signal In the case of a single word transmission after all bits of the data word are transferred the SSEL line is returned to its idle HIGH state one SCK period...

Page 287: ...ctive transmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SCK signal After all bi...

Page 288: ...LOW CS is forced HIGH The transmit data line SO is arbitrarily forced LOW A transmission is triggered by writing a control byte to the transmit FIFO The falling edge of CS causes the value contained i...

Page 289: ...he control byte of the next frame follows directly after the LSB of the received data from the current frame Each of the received values is transferred from the receive shifter on the falling edge SK...

Page 290: ...g masters without corruption of serial data on the bus Programmable clock allows adjustment of I2C transfer rates Data transfer is bidirectional between masters and slaves Serial clock synchronization...

Page 291: ...ast received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a Repeate...

Page 292: ...eeded 0xF8 Table 272 DAT R W 0x008 I2C Data Register During master or slave transmit mode data to be transmitted is written to this register During master or slave receive mode data that has been rece...

Page 293: ...to the DATA_BUFFER automatically after every nine bits 8 bits of data plus ACK or NACK has been received on the bus 0x00 Table 281 MASK0 R W 0x030 I2C Slave address mask register 0 This mask register...

Page 294: ...writing 1 to the STAC bit in the CONCLR register When STA is 0 no START condition or Repeated START condition will be generated If STA and STO are both set then a STOP condition is transmitted on the...

Page 295: ...least significant bits are always 0 Taken as a byte the status register contents represent a status code There are 26 possible status codes When the status code is 0xF8 there is no relevant informati...

Page 296: ...L HIGH time SCLL defines the number of I2C_PCLK cycles for the SCL low time The frequency is determined by the following formula I2C_PCLK is the frequency of the peripheral I2C clock 4 The values for...

Page 297: ...CONSET register Writing 0 has no effect I2ENC is the I2C Interface Disable bit Writing a 1 to this bit clears the I2EN bit in the CONSET register Writing 0 has no effect 14 7 7 I2C Monitor mode contr...

Page 298: ...er Table 279 I2C Monitor mode control register MMCTRL 0x4000 001C bit description Bit Symbol Value Description Reset value 0 MM_ENA Monitor mode enable 0 0 Monitor mode disabled 1 The I2C module will...

Page 299: ...s contain 0x00 the I2C will not acknowledge any address on the bus All four registers will be cleared to this disabled state on reset also see Table 274 14 7 9 I2C Data buffer register DATA_BUFFER In...

Page 300: ...1 8 and bit 0 of the mask registers are unused and should not be written to These bits will always read back as zeros When an address match interrupt occurs the processor will have to read the data re...

Page 301: ...special pad designed to conform to the I2C specification Fig 41 I2C serial interface block diagram APB BUS STATUS REGISTER I2CnSTAT CONTROL REGISTER and SCL DUTY CYLE REGISTERS I2CnCONSET I2CnCONCLR I...

Page 302: ...he first received 8 bit byte with the General Call address 0x00 If an equality is found the appropriate status bits are set and an interrupt is requested 14 8 5 Shift register DAT This 8 bit register...

Page 303: ...mable clock pulse generator provides the SCL clock pulses when the I2C block is in the master transmitter or master receiver mode It is switched off when the I2C block is in slave mode The I2C output...

Page 304: ...ach I2C bus status The 5 bit code may be used to generate vector addresses for fast processing of the various service routines Each service routine processes a particular bus status There are 26 possi...

Page 305: ...to vector to a state service routine which will load the slave address and Write bit to the DAT register and then clear the SI bit SI is cleared by writing a 1 to the SIC bit in the CONCLR register Wh...

Page 306: ...4 I2EN must be set to 1 to enable the I2C function AA bit must be set to 1 to acknowledge its own slave address or the General Call address The STA STO and SI bits are set to 0 After ADR and CONSET ar...

Page 307: ...I2C hardware looks for its own slave address and the General Call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become the bus master the...

Page 308: ...ervice routine For each status code the required software action and details of the following serial transfer are given in tables from Table 287 to Table 293 14 10 1 Master Transmitter mode In the mas...

Page 309: ...sed by the interrupt service routine to enter the appropriate state service routine that loads DAT with the slave address and the data direction bit SLA W The SI bit in CON must then be reset before t...

Page 310: ...n received Load data byte or 0 0 0 X Data byte will be transmitted ACK bit will be received No DAT action or 1 0 0 X Repeated START will be transmitted No DAT action or 0 1 0 X STOP condition will be...

Page 311: ...A A OR A A other Master continues other Master continues A other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Data byte Not Acknowledge received a...

Page 312: ...routine must load DAT with the 7 bit slave address and the data direction bit SLA R The SI bit in CON must then be cleared before the serial transfer can continue When the slave address and the data d...

Page 313: ...en the bus becomes free 0x40 SLA R has been transmitted ACK has been received No DAT action or 0 0 0 0 Data byte will be received NOT ACK bit will be returned No DAT action 0 0 0 1 Data byte will be r...

Page 314: ...S W A A OR A A P other Master continues other Master continues A other Master continues 48H 40H 58H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Acknowledge bit Not Acknowledge receive...

Page 315: ...by its own slave address followed by the data direction bit which must be 0 W for the I2C block to operate in the slave receiver mode After its own slave address and the W bit have been received the s...

Page 316: ...ned No DAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No DAT action X 0 0 1 Data byte will be received and ACK will be returned 0x80 Previously addressed with own SLV ad...

Page 317: ...call address will be recognized if ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or Repeated START condition has been received while still addres...

Page 318: ...or more Data bytes arbitration lost as Master and addressed as Slave last data byte received is Not acknowledged arbitration lost as Master and addressed as Slave by General Call reception of the own...

Page 319: ...set and a valid status code can be read from STAT This status code is used to vector to a state service routine and the appropriate action to be taken for each of these status codes is detailed in Ta...

Page 320: ...ed NOT ACK has been received No DAT action or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address No DAT action or 0 0 0 1 Switched to not addressed SLV mode O...

Page 321: ...sed when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge...

Page 322: ...peated START condition see Figure 53 Until this occurs arbitration is not lost by either master since they were both transmitting the same data If the I2C hardware detects a Repeated START condition o...

Page 323: ...sible for an uncontrolled source to cause a bus hang up In such situations the problem may be caused by interference temporary interruption of the bus or a temporary short circuit between SDA and SCL...

Page 324: ...chronization so a START should be generated to insure that all I2C peripherals are synchronized 14 10 6 5 Bus error A bus error occurs when a START or STOP condition is detected at an illegal position...

Page 325: ...n 14 10 9 I2C interrupt service When the I2C interrupt is entered STAT contains a status code which identifies one of the 26 state services to be executed 14 10 10 The state service routines Each stat...

Page 326: ...Receive buffer 5 Initialize the Master data counter to match the length of the message to be received 6 Exit 14 11 4 I2C interrupt routine Determine the I2C state and which state routine will be used...

Page 327: ...8 or State 10 Slave Address Write has been transmitted ACK has been received The first data byte will be transmitted an ACK bit will be received 1 Load DAT with first data byte from Master Transmit b...

Page 328: ...to CONSET to set the STA and AA bits 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 14 11 7 Master Receive states 14 11 7 1 State 0x40 Previous state was State 08 or State 10 Slave Address Read ha...

Page 329: ...ress Write has been received ACK has been returned Data will be received and ACK returned 1 Write 0x04 to CONSET to set the AA bit 2 Write 0x08 to CONCLR to clear the SI flag 3 Set up Slave Receive mo...

Page 330: ...eturned Additional data will be read 1 Read data byte from DAT into the Slave Receive buffer 2 Decrement the Slave data counter skip to step 5 if not the last data byte 3 Write 0x0C to CONCLR to clear...

Page 331: ...wn Slave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received 1 Load DAT from Slave Transmit buffer with first data byte 2 Write 0x04 to CONSET to set...

Page 332: ...o CONCLR to clear the SI flag 4 Increment Slave Transmit buffer pointer 5 Exit 14 11 9 4 State 0xC0 Data has been transmitted NOT ACK has been received Not addressed Slave mode is entered 1 Write 0x04...

Page 333: ...6 bit counter timers with a programmable 16 bit prescaler Counter or timer operation Two 16 bit capture channels that can take a snapshot of the timer value when an input signal transitions A capture...

Page 334: ...ut pins It is recommended to use the match registers that are not pinned out to control the PWM cycle length 15 6 Pin description Table 294 gives a brief summary of each of the counter timer related p...

Page 335: ...able through the bus interface 0 Table 302 MCR R W 0x014 Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs 0 Table 303 MR0 R W 0...

Page 336: ...14 Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs 0 Table 303 MR0 R W 0x018 Match Register 0 MR0 can be enabled through the M...

Page 337: ...l the operation of the counter timer Table 297 Interrupt Register IR address 0x4000 C000 CT16B0 bit description Bit Symbol Description Reset value 0 MR0INT Interrupt flag for match channel 0 0 1 MR1IN...

Page 338: ...and the maximum time before the timer overflows The Prescale Counter is incremented on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Pr...

Page 339: ...014 CT16B0 and 0x4001 0014 CT16B1 bit description Bit Symbol Value Description Reset value 0 MR0I Interrupt on MR0 an interrupt is generated when MR0 matches the value in the TC 0 1 Enabled 0 Disabled...

Page 340: ...description below n represents the Timer number 0 or 1 Remark The bit positions for the CAP1 channel control bits are different for counter timers CT16B0 bits 8 6 Table 305 and CT16B1 bits 5 3 Table...

Page 341: ...equence of 0 then 1 on CT16B0_CAP1 will cause CR1 to be loaded with the contents of TC This bit is reserved for 16 bit timer1 CT16B1 0 1 Enabled 0 Disabled 7 CAP1FE Capture on CT16B0_CAP1 falling edge...

Page 342: ...interrupt 0 1 Enabled 0 Disabled 3 CAP1RE Capture on CT16B1_CAP1 rising edge a sequence of 0 then 1 on CT16B1_CAP1 will cause CR1 to be loaded with the contents of TC 0 1 Enabled 0 Disabled 4 CAP1FE...

Page 343: ...t is driven to the CT16B0_MAT0 CT16B1_MAT0 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH 0 1 EM1 External Match 1 This bit reflects the state of output CT16B0_MAT1 CT16B1_...

Page 344: ...Bn_MAT1 pin is HIGH if pinned out 0x3 Toggle the corresponding External Match bit output 9 8 EMC2 External Match Control 2 Determines the functionality of External Match 2 00 0x0 Do Nothing 0x1 Clear...

Page 345: ...ubtraction operation in software Remark The bit positions for the CAP1 channel count input select CIS and edge select bits SELCC are different for counter timers CT16B0 Table 312 and CT16B1 Table 313...

Page 346: ...x4001 0070 CT16B1 bit description Bit Symbol Value Description Reset value 1 0 CTM Counter Timer Mode This field selects which rising PCLK edges can increment Timer s Prescale Counter PC or clear PC a...

Page 347: ...4 is a 1 these bits select which capture input edge will cause the timer and prescaler to be cleared These bits have no effect when bit 4 is low Values 0x6 to 0x7 are reserved 0 0x0 Rising Edge of CT...

Page 348: ...st of a one clock tick wide positive pulse with a period determined by the PWM cycle length i e the timer reload value 5 If a match register is set to zero then the PWM output will go to HIGH the firs...

Page 349: ...next clock after the timer reached the match value Figure 58 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the...

Page 350: ...imers CT16B0 1 Fig 59 16 bit counter timer block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable CAPTURE REGISTER 0 MATCH REGISTER 3 MATCH REGISTER 2 MATCH R...

Page 351: ...Section 16 7 1 Interrupt Register Section 16 7 8 Capture Control Register Section 16 7 9 Capture Registers Section 16 7 11 Count Control Register 16 3 Features Two 32 bit counter timers with a program...

Page 352: ...gisters can be used to provide a single edge controlled PWM output on the match output pins One match register is used to control the PWM cycle length 16 6 Pin description Table 315 gives a brief summ...

Page 353: ...ervable and controllable through the bus interface 0 Table 323 MCR R W 0x014 Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs 0...

Page 354: ...vable and controllable through the bus interface 0 Table 323 MCR R W 0x014 Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs 0 T...

Page 355: ...318 Interrupt Register IR address 0x4001 4000 CT32B0 bit description Bit Symbol Description Reset value 0 MR0INT Interrupt flag for match channel 0 0 1 MR1INT Interrupt flag for match channel 1 0 2 MR...

Page 356: ...ounter is incremented on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to...

Page 357: ...ches it 0 1 Enabled 0 Disabled 2 MR0S Stop on MR0 the TC and PC will be stopped and TCR 0 will be set to 0 if MR0 matches the TC 0 1 Enabled 0 Disabled 3 MR1I Interrupt on MR1 an interrupt is generate...

Page 358: ...s are different for counter timers CT32B0 bits 8 6 Table 326 and CT32B1 bits 5 3 Table 327 11 MR3S Stop on MR3 the TC and PC will be stopped and TCR 0 will be set to 0 if MR3 matches the TC 0 1 Enable...

Page 359: ...NA Table 326 Capture Control Register CCR address 0x4001 4028 CT32B0 bit description Bit Symbol Value Description Reset value Table 327 Capture Control Register CCR address 0x4001 8028 CT32B1 bit desc...

Page 360: ...f the external match pins CAP32Bn_MAT 3 0 If the match outputs are configured as PWM output the function of the external match registers is determined by the PWM rules Section 16 7 13 Rules for single...

Page 361: ...ts EMR 9 8 control the functionality of this output This bit is driven to the CT32B0_MAT2 CT32B1_MAT2 pins if the match function is selected in the IOCON registers 0 LOW 1 HIGH 0 3 EM3 External Match...

Page 362: ...e CAP input in this case cannot be shorter than 1 PCLK Bits 7 4 of this register are also used to enable and configure the capture clears timer feature This feature allows for a designated edge on a p...

Page 363: ...elected by bits 3 2 0x3 Counter Mode TC is incremented on both edges on the CAP input selected by bits 3 2 3 2 CIS Count Input Select In counter mode when bits 1 0 in this register are not 00 these bi...

Page 364: ...00 00 0x0 Timer Mode every rising PCLK edge 0x1 Counter Mode TC is incremented on rising edges on the CAP input selected by bits 3 2 0x2 Counter Mode TC is incremented on falling edges on the CAP inpu...

Page 365: ...e same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick after the timer reaches the match value Therefore the PWM output will always...

Page 366: ...ch register set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is g...

Page 367: ...Semiconductors UM10462 Chapter 16 LPC11U3x 2x 1x 32 bit counter timers CT32B0 1 16 9 Architecture The block diagram for 32 bit counter timer0 and 32 bit counter timer1 is shown in Figure 63 Fig 62 A t...

Page 368: ...mers CT32B0 1 Fig 63 32 bit counter timer block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable CAPTURE REGISTER 1 CAPTURE REGISTER 0 MATCH REGISTER 3 MATCH...

Page 369: ...ut period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Programmable 24 bit timer with internal fixed pre scaler Selectable time perio...

Page 370: ...TWDCLK 256 4 and the maximum Watchdog interval is TWDCLK 224 4 in multiples of TWDCLK 4 The Watchdog should be used in the following manner Set the Watchdog timer constant reload value in the TC regis...

Page 371: ...s follows When the MOD and TC registers are updated by APB operations the new value will take effect in 3 WDCLK cycles on the logic in the WDCLK clock domain When the watchdog timer is counting on WDC...

Page 372: ...k source for each power mode is selected before setting bit 5 in the MOD register Active or Sleep modes Both the IRC or the watchdog oscillator are allowed Deep sleep mode Both the IRC and the watchdo...

Page 373: ...iting 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC NA Table 340 TV RO 0x00C Watchdog timer value register This 24 bit register reads out the curre...

Page 374: ...a watchdog interrupt occurs in Sleep Deep sleep mode or Power down mode and the WWDT interrupt is enabled in the NVIC the device will wake up Note that in Deep sleep and Power down modes the WWDT inte...

Page 375: ...dog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following an incorrect access to a Watchdog register during a feed sequence It is good practise to disable int...

Page 376: ...e bottom 10 bits of the counter have the same value as the 10 bits of WARNINT and the remaining upper bits of the counter are all 0 This gives a maximum time of 1 023 watchdog timer counts 4 096 watch...

Page 377: ...es illustrate several aspects of Watchdog Timer operation Table 343 Watchdog Timer Warning Interrupt register WARNINT 0x4000 4014 bit description Bit Symbol Description Reset Value 9 0 WARNINT Watchdo...

Page 378: ...atchdog Timer WWDT Fig 66 Correct Watchdog Feed with Windowed Mode Enabled Correct Feed Event 1201 11FF 1200 WDCLK 4 Watchdog Counter Watchdog Reset 11FC 11FD 2000 1FFE 1FFF 11FE 1FFD 1FFC Conditions...

Page 379: ...he SysTick timer in the SYST_CSR register Table 452 18 3 Features Simple 24 bit timer Uses dedicated exception vector Clocked internally by the system clock or the system clock 2 18 4 General descript...

Page 380: ...to the Cortex M0 User Guide for details 18 5 Register description The systick timer registers are located on the ARM Cortex M0 private peripheral bus see Figure 4 and are part of the ARM Cortex M0 cor...

Page 381: ...enabled the interrupt is generated when the System Tick counter counts down to 0 0 2 CLKSOURCE System Tick clock source selection When 1 the system clock CPU clock is selected When 0 the system clock...

Page 382: ...ault value gives a 10 millisecond interrupt rate if the CPU clock is set to 50 MHz 18 7 Example timer calculations To use the system tick timer do the following 1 Program the SYST_RVR register with th...

Page 383: ...ximation process An accurate conversion requires 11 clock cycles 19 3 Features 10 bit successive approximation Analog to Digital Converter ADC Input multiplexing among 8 pins Power down mode Measureme...

Page 384: ...that allow the DONE flag of each A D channel to be included or excluded from contributing to the generation of an A D interrupt 0x0000 0100 Table 354 DR0 R W 0x010 A D Channel 0 Data Register This reg...

Page 385: ...or slightly less but in certain cases such as a high impedance analog source a slower clock may be desirable 0 16 BURST Burst mode Remark If BURST is set to 1 the ADGINTEN bit in the INTEN register T...

Page 386: ...d contains 010 111 In these cases 0 0 Start conversion on a rising edge on the selected CAP MAT signal 1 Start conversion on a falling edge on the selected CAP MAT signal 31 28 Reserved user software...

Page 387: ...TEN address 0x4001 C00C bit description Bit Symbol Description Reset Value 7 0 ADINTEN These bits allow control over which A D channels generate interrupts for conversion completion When bit 0 is one...

Page 388: ...ster for an A D channel that is generating an interrupt must be read in order to clear the corresponding DONE flag 19 6 3 Accuracy vs digital receiver While the A D converter can be used to measure th...

Page 389: ...no no yes no LPC11U14FHI33 201 32 Table 360 no no yes no LPC11U14FET48 201 32 Table 360 no no yes no LPC11U22FBD48 301 16 Table 360 no 1 yes yes LPC11U23FBD48 301 24 Table 360 no 1 yes yes LPC11U24FH...

Page 390: ...ured through a register in the flash controller block Erase time for one sector is 100 ms 5 Programming time for one block of 256 bytes is 1 ms 5 Support for ISP via the USB port through enumeration a...

Page 391: ...ibed later in this chapter The interrupt vectors residing in the boot block of the on chip flash memory also become active after reset i e the bottom 512 bytes of the boot block are also visible in th...

Page 392: ...ith the host via the serial port UART If the UART is selected the host should send a 0x3F as a synchronization character and wait for a response The host side serial port settings should be 8 data bit...

Page 393: ...f binary data in to 2 bytes of ASCII hex The sender should send the check sum after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can...

Page 394: ...rted parts The LPC11U3x 2x 1x is enumerated as a Mass Storage Class MSC device to a PC or another embedded system In order to connect via the USB interface the LPC11U3x 2x 1x must use the external cry...

Page 395: ...st be either part of the vector table or the axf or binary file must be post processed to insert the checksum Table 359 CRP levels for USB boot images CRP status Volume label Description No CRP CRP DI...

Page 396: ...14 8 2 For details on available ISP commands based on the CRP settings see Section 20 12 Fig 69 Boot process flowchart RESET INITIALIZE RECEIVE CRYSTAL FREQUENCY RUN ISP COMMAND HANDLER RUN AUTO BAUD...

Page 397: ...0000 2000 0x0000 2FFF yes yes yes 3 4 0x0000 3000 0x0000 3FFF yes yes yes 4 4 0x0000 4000 0x0000 4FFF yes yes 5 4 0x0000 5000 0x0000 5FFF yes yes 6 4 0x0000 6000 0x0000 6FFF yes 7 4 0x0000 7000 0x0000...

Page 398: ...56 271 0x0001 0000 0x0001 0FFF no no no yes yes 17 4 272 287 0x0001 1000 0x0001 1FFF no no no yes yes 18 4 288 303 0x0001 2000 0x0001 2FFF no no no yes yes 19 4 304 319 0x0001 3000 0x0001 3FFF no no n...

Page 399: ...l sectors can not be erased Since compare command is disabled in case of partial updates the secondary loader should implement checksum mechanism to verify the integrity of the flash CRP2 0x87654321 A...

Page 400: ...allowed in NO_ISP mode but disabled in CRP3 mode The NO_ISP mode does not offer any code protection CRP2 Yes High No No NA CRP2 Yes Low No Yes No CRP3 Yes x No No NA CRP1 No x No Yes Yes CRP2 No x No...

Page 401: ...ode Table 365 ISP command summary ISP Command Usage Described in Unlock U Unlock Code Table 366 Set Baud Rate B Baud Rate stop bit Table 367 Echo A setting Table 368 Write to RAM W start address numbe...

Page 402: ...he actual number of bytes sent The ISP command handler compares it with the check sum of the received bytes If the check sum matches the ISP command handler responds with OK CR LF to continue further...

Page 403: ...r This command makes flash write erase operation a two step process Table 369 ISP Write to RAM command Command W Input Start Address RAM address where data bytes are to be written This address should...

Page 404: ...memories an erase should be performed after following 16 consecutive writes inside the same page Note that the erase operation then erases the entire sector Remark Once a page has been written to 16 t...

Page 405: ...Input Flash Address DST Destination flash address where data bytes are to be written The destination address should be a 256 byte boundary RAM Address SRC Source RAM address from where data bytes are...

Page 406: ...ED Description This command is used to execute a program residing in RAM or flash memory It may not be possible to return to the ISP command handler once this command is successfully executed This com...

Page 407: ...rns 0 for the offset and value of sectors which are not blank Blank sectors are correctly reported irrespective of the CRP setting Example I 2 3 CR LF blank checks the flash sectors 2 and 3 Table 376...

Page 408: ...wed by 2 bytes of boot code version number in ASCII format It is to be interpreted as byte1 Major byte0 Minor Description This command is used to read the boot code version number Table 379 ISP Compar...

Page 409: ...PED Source address is not mapped in the memory map Count value is taken in to consideration where applicable 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map Count value is ta...

Page 410: ...of parameters is 5 passed to the Copy RAM to FLASH command The maximum number of results is 4 returned by the ReadUID command The command handler sends the status code INVALID_COMMAND when an undefine...

Page 411: ...e in the C compiler implementation from different vendors The suggested parameter passing scheme reduces such risk The flash memory is not accessible during a write or erase operation IAP commands whi...

Page 412: ...1 Result n Command Parameter Array Status Result Array ARM REGISTER r0 ARM REGISTER r1 command_param 0 command_param 1 command_param 2 command_param n status_result 2 status_result n Table 383 IAP Pr...

Page 413: ..._NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 256 512 1024 4096 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY Result None Description This command is used to program the flash memory Th...

Page 414: ...non blank word location if the status code is SECTOR_NOT_BLANK Result1 Contents of non blank word location Description This command is used to blank check a sector or multiple sectors of on chip flas...

Page 415: ...f the status code is COMPARE_ERROR Description This command is used to compare the memory contents at two locations The result may not be correct when the source or destination includes any of the fir...

Page 416: ...and end page numbers See Table 357 for list of parts that implement this command Table 393 IAP Write EEPROM command Command Compare Input Command code 61 decimal Param0 EEPROM address Param1 RAM addre...

Page 417: ...RAM to flash repeatedly with proper offset Table 395 IAP Status codes summary Status code Mnemonic Description 0 CMD_SUCCESS Command is executed successfully 1 INVALID_COMMAND Invalid command 2 SRC_AD...

Page 418: ...0x4003 C000 Name Access Address offset Description Reset value Reference FLASHCFG R W 0x010 Flash memory access time configuration register Table 401 FMSSTART R W 0x020 Signature start address registe...

Page 419: ...e select bit 0 the BIST signature is generated over the total memory space Singe pages are interleaved over the EEPROM devices when multiple devices are used the signature is generated over memory of...

Page 420: ...ontents The address range to be used for generation is defined by writing the start address to the signature start address register FMSSTART and the stop address to the signature stop address register...

Page 421: ...egister SIG_DONE should be cleared via the FMSTATCLR register before starting a signature generation operation otherwise the status might indicate completion of a previous operation Table 403 Flash mo...

Page 422: ...x FMSSTOP FMSSTART 1 When signature generation is triggered via software the duration is in AHB clock cycles and tcy is the time in ns for one AHB clock The SIG_DONE bit in FMSTAT can be polled by so...

Page 423: ...FMSW0 to FMSW3 registers must be equal to the reference signature The algorithms to derive the reference signature is given in Figure 71 Fig 71 Algorithm for generating a 128 bit signature int128 sig...

Page 424: ...red to support up to four breakpoints and two watchpoints 21 4 Description Debugging with the LPC11U3x 2x 1x uses the Serial Wire Debug mode Support for boundary scan is available 21 5 Pin description...

Page 425: ...d to recover the part from configurations which would disable the SWD port such as improper PLL configuration reconfiguration of SWD pins as ADC inputs entry into Deep power down mode out of reset etc...

Page 426: ...in pulled HIGH externally 3 Wait for at least 250 s 4 Pull the RESET pin LOW externally 5 Perform boundary scan operations 6 Once the boundary scan operations are completed assert the TRST pin to enab...

Page 427: ...ad and operators in C 22 3 Description The API calls to the ROM are performed by executing functions which are pointed by a pointer within the ROM Driver Table Figure 73 shows the pointer structure us...

Page 428: ...signed integer division unsigned uidiv unsigned numerator unsigned denominator Signed integer division with remainder idiv_return sidivmod int numerator int denominator Unsigned integer division with...

Page 429: ...UM10462 Chapter 22 LPC11U3x 2x 1x Integer division routines result pDivROM sidiv 99 6 result now contains 16 22 4 3 Unsigned division with remainder The example C code listing below shows how to perf...

Page 430: ...ware library on http www LPCware com lists the IOH_n pin functions and other pin functions if necessary that must be selected in the IOCON block 23 4 Description The I O Handler is a software library...

Page 431: ...RT The emulated UART can be configured for 7 or 8 data bits no parity and 1 or 2 stop bits The baud rate is configurable up to 115200 baud The RXD signal is available on three I O Handler pins IOH_6 I...

Page 432: ...y The Cortex M0 processor is built on a highly area and power optimized 32 bit processor core with a 3 stage pipeline von Neumann architecture The processor delivers exceptional energy efficiency thro...

Page 433: ...hat enables the entire device to be rapidly powered down 24 2 1 System level interface The Cortex M0 processor provides a single system level interface using AMBA technology to provide high speed low...

Page 434: ...e processor returns to Thread mode when it has finished all exception processing 24 3 1 2 Stacks The processor uses a full descending stack This means the stack pointer indicates the last stacked item...

Page 435: ...tack pointer to use 0 Main Stack Pointer MSP This is the reset value 1 Process Stack Pointer PSP Fig 75 Processor core register set Table 413 Core register set summary Name Type 1 Reset value Descript...

Page 436: ...er The Program Status Register PSR combines Application Program Status Register APSR Interrupt Program Status Register IPSR Execution Program Status Register EPSR These registers are mutually exclusiv...

Page 437: ...egative zero carry or borrow and overflow flags Interrupt Program Status Register The IPSR contains the exception number of the current Interrupt Service Routine ISR See the register summary in Table...

Page 438: ...abandons execution of the instruction After servicing the interrupt the processor restarts execution of the instruction from the beginning 24 3 1 3 6 Exception mask register The exception mask regist...

Page 439: ...ex M0 processor supports interrupts and system exceptions The processor and the Nested Vectored Interrupt Controller NVIC prioritize and handle all exceptions An interrupt or exception changes the nor...

Page 440: ...ation of CMSIS compliant software components from various middleware vendors Software vendors can expand the CMSIS to include their peripheral definitions and access functions for those peripherals Th...

Page 441: ...memory map is split into regions Each region has a defined memory type and some regions have additional memory attributes The memory type and attributes determine the behavior of accesses to the regi...

Page 442: ...order in which the accesses complete matches the program order of the instructions providing any re ordering does not affect the behavior of the instruction sequence Normally if correct program execu...

Page 443: ...MB The Data Memory Barrier DMB instruction ensures that outstanding memory transactions complete before subsequent memory transactions See Section 24 24 4 7 3 DSB The Data Synchronization Barrier DSB...

Page 444: ...nstruction execution uses the updated memory map Memory accesses to Strongly ordered memory such as the System Control Block do not require the use of DMB instructions The processor preserves transact...

Page 445: ...ly enabled and has a fixed priority of 2 NMIs cannot be masked or prevented from activation by any other exception preempted by any exception other than Reset HardFault A HardFault is an exception tha...

Page 446: ...2 3 For more information about HardFaults see Section 24 24 3 4 24 3 3 3 Exception handlers The processor handles exceptions using Interrupt Service Routines ISRs Interrupts IRQ0 to IRQ31 are the exc...

Page 447: ...rity configurable priorities for all exceptions except Reset HardFault and NMI If software does not configure any priorities then all exceptions with a configurable priority have a priority of 0 For i...

Page 448: ...exceptions are called nested exceptions See Section 24 24 3 3 6 1 for more information Return This occurs when the exception handler is completed and there is no pending exception with sufficient pri...

Page 449: ...plete the processor starts executing the exception handler At the same time the processor writes an EXC_RETURN value to the LR This indicates which stack pointer corresponds to the stack frame and wha...

Page 450: ...rror on a vector fetch execution of an Undefined instruction execution of an instruction when not in Thumb State as a result of the T bit being previously cleared to 0 an attempted load or store to an...

Page 451: ...ck into sleep mode after such an event A program might have an idle loop to put the processor back in to sleep mode 24 3 5 1 1 Wait for interrupt The Wait For Interrupt instruction WFI causes immediat...

Page 452: ...f an interrupt arrives that is enabled and has a higher priority than current exception priority the processor wakes up but does not execute the interrupt handler until the processor sets PRIMASK to z...

Page 453: ...1 ANDS Rd Rn Rm Bitwise AND N Z Section 24 24 4 5 1 ASRS Rd Rm Rs imm Arithmetic Shift Right N Z C Section 24 24 4 5 3 B cc label Branch conditionally Section 24 24 4 6 1 BICS Rd Rn Rm Bit Clear N Z...

Page 454: ...eg Move to general register from special register Section 24 24 4 7 6 MSR spec_reg Rm Move to special register from general register N Z C V Section 24 24 4 7 7 MULS Rd Rn Rm Multiply 32 bit result N...

Page 455: ...Store Register as byte Section 24 24 4 4 STRH Rt Rn Rm imm Store Register as halfword Section 24 24 4 4 SUB S Rd Rn Rm imm Subtract N Z C V Section 24 24 4 5 1 SVC imm Supervisor Call Section 24 24 4...

Page 456: ...ds 24 4 3 2 Restrictions when using PC or SP Many instructions are unable to use or have restrictions on whether you can use the Program Counter PC or Stack Pointer SP for the operands or destination...

Page 457: ...ithmetic shift right by n bits moves the left hand 32 n bits of the register Rm to the right by n places into the right hand 32 n bits of the result and it copies the original bit 31 of the register i...

Page 458: ...Rm by 2n if the value is regarded as an unsigned integer or a two s complement signed integer Overflow can occur without warning When the instruction is LSLS the carry flag is updated to the last bit...

Page 459: ...struction or literal data It is represented in the instruction as the PC value plus or minus a numeric offset The assembler calculates the required offset from the label and the address of the current...

Page 460: ...ction Overflow occurs when the sign of the result in bit 31 does not match the sign of the result had the operation been performed at infinite precision for example if adding two negative values resul...

Page 461: ...ero VS V 1 Overflow VC V 0 No overflow HI C 1 and Z 0 Higher unsigned LS C 0 or Z 1 Lower or same unsigned GE N V Greater than or equal signed LT N V Less than signed GT Z 0 and N V Greater than signe...

Page 462: ...extMessage to R1 ADR R3 PC 996 Set R3 to value of PC 996 24 4 4 2 LDR and STR immediate offset Load and Store with immediate offset 24 4 4 2 1 Syntax LDR Rt Rn SP imm LDR B H Rt Rn imm STR Rt Rn SP im...

Page 463: ...LDR R4 R7 Loads R4 from the address in R7 STR R2 R0 const struc const struc is an expression evaluating to a constant in the range 0 1020 24 4 4 3 LDR and STR register offset Load and Store with regi...

Page 464: ...nd R1 LDRSH R1 R2 R3 Load a halfword from the memory address specified by R2 R3 sign extend to 32 bits and write to R1 24 4 4 4 LDR PC relative Load register literal from memory 24 4 4 4 1 Syntax LDR...

Page 465: ...s in reglist with word values from memory addresses based on Rn STM instructions store the word values in the registers in reglist to memory addresses based on Rn The memory addresses used for the acc...

Page 466: ...ng the lowest memory address and the highest numbered register using the highest memory address POP loads registers from the stack with the lowest numbered register using the lowest memory address and...

Page 467: ...al AND Section 24 24 4 5 2 ASRS Arithmetic Shift Right Section 24 24 4 5 3 BICS Bit Clear Section 24 24 4 5 2 CMN Compare Negative Section 24 24 4 5 4 CMP Compare Section 24 24 4 5 4 EORS Exclusive OR...

Page 468: ...dds the value in Rn to the value in Rm or an immediate value specified by imm and places the result in the register specified by Rd The ADDS instruction performs the same operation as ADD and also upd...

Page 469: ...th carry SBCS R6 R6 R3 subtract the most significant words with carry The following shows the RSBS instruction used to perform a 1 s complement of a single register Arithmetic negation RSBS R7 R7 0 su...

Page 470: ...IC instruction performs an AND operation on the bits in Rn with the logical negation of the corresponding bits in the value of Rm The condition code flags are updated on the result of the operation se...

Page 471: ...a right rotation of the bits in the register Rm by the number of places specified by the immediate imm or the value in the least significant byte of the register specified by Rs For details on what re...

Page 472: ...Rm or the immediate imm from the value in Rn and updates the flags This is the same as a SUBS instruction except that the result is discarded The CMN instruction adds the value of Rm to the value in...

Page 473: ...carded A branch occurs to the address created by forcing bit 0 of the result to 0 The T bit remains unmodified Remark Though it is possible to use MOV as a branch instruction ARM strongly recommends t...

Page 474: ...5 6 4 Condition flags This instruction updates the N and Z flags according to the result does not affect the C or V flags 24 4 5 6 5 Examples MULS R0 R2 R0 Multiply with flag update R0 R0 x R2 24 4 5...

Page 475: ...UXTH Rd Rm where Rd is the destination register Rm is the register holding the value to be extended 24 4 5 8 2 Operation These instructions extract bits from the resulting value SXTB extracts bits 7 0...

Page 476: ...lt To test whether a bit of Rn is 0 or 1 use the TST instruction with a register that has that bit set to 1 and all other bits cleared to 0 24 4 5 9 3 Restrictions In these instructions Rn and Rm must...

Page 477: ...0 of Rm is 0 BL and BLX instructions also set bit 0 of the LR to 1 This ensures that the value is suitable for use by a subsequent POP PC or BX instruction to perform a successful return branch Table...

Page 478: ...tax BKPT imm where imm is an integer in the range 0 255 Table 432 Miscellaneous instructions Mnemonic Brief description See BKPT Breakpoint Section 24 24 4 7 1 CPSID Change Processor State Disable Int...

Page 479: ...is executed See Section 24 24 3 4 1 for more information 24 4 7 1 3 Restrictions There are no restrictions 24 4 7 1 4 Condition flags This instruction does not change the flags 24 4 7 1 5 Examples BKP...

Page 480: ...change the flags 24 4 7 3 5 Examples DMB Data Memory Barrier 24 4 7 4 DSB Data Synchronization Barrier 24 4 7 4 1 Syntax DSB 24 4 7 4 2 Operation DSB acts as a special data synchronization memory bar...

Page 481: ...pec_reg is one of the special purpose registers APSR IPSR EPSR IEPSR IAPSR EAPSR PSR MSP PSP PRIMASK or CONTROL 24 4 7 6 2 Operation MRS stores the contents of a special purpose register to a general...

Page 482: ...ates the flags explicitly based on the value in Rn 24 4 7 7 5 Examples MSR CONTROL R1 Read R1 value and write it to the CONTROL register 24 4 7 8 NOP No Operation 24 4 7 8 1 Syntax NOP 24 4 7 8 2 Oper...

Page 483: ...er in the range 0 255 24 4 7 10 2 Operation The SVC instruction causes the SVC exception imm is ignored by the processor If required it can be retrieved by the exception handler to determine what serv...

Page 484: ...ely For more information see Section 24 24 3 5 Remark WFE is intended for power saving only When writing software assume that WFE might behave as NOP 24 4 7 11 3 Restrictions There are no restrictions...

Page 485: ...n of interrupt signals Interrupt tail chaining An external Non maskable interrupt NMI The processor automatically stacks its state on exception entry and unstacks this state on exception exit with no...

Page 486: ...e Register The ICER disables interrupts and show which interrupts are enabled See the register summary in Table 24 434 for the register attributes The bit assignments are Table 435 CMISIS acess NVIC f...

Page 487: ...er The ICPR removes the pending state from interrupts and shows which interrupts are pending See the register summary in Table 24 434 for the register attributes The bit assignments are Remark Writing...

Page 488: ...to register bits 7 0 byte offset 1 refers to register bits 15 8 byte offset 2 refers to register bits 23 16 byte offset 3 refers to register bits 31 24 24 5 2 7 Level sensitive and pulse interrupts T...

Page 489: ...r enters the ISR for the interrupt This changes the state of the interrupt from pending to active Then For a level sensitive interrupt when the processor returns from the ISR the NVIC samples the inte...

Page 490: ...cy the CMSIS simplifies the SCB register presentation In the CMSIS the array SHP 1 corresponds to the registers SHPR2 SHPR3 24 5 3 2 CPUID Register The CPUID register contains the processor part numbe...

Page 491: ...tion being processed whether there are preempted active exceptions the exception number of the highest priority pending exception whether any interrupts are pending See the register summary in Table 2...

Page 492: ...y the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler 30 29 Reserved 28 PENDSVSET RW PendSV set pending bit Write 0 no effect 1 chang...

Page 493: ...ents are 22 ISRPENDING RO Interrupt pending flag excluding NMI and Faults 0 interrupt not pending 1 interrupt pending 21 18 Reserved 17 12 VECTPENDING RO Indicates the exception number of the highest...

Page 494: ...therwise behavior is Unpredictable 0 Reserved Table 445 AIRCR bit assignments Bits Name Type Function Table 446 SCR bit assignments Bits Name Function 31 5 Reserved 4 SEVONPEND Send Event on Pending b...

Page 495: ...handler are Each PRI_N field is 8 bits wide but the processor implements only bits 7 6 of each field and bits 5 0 read as zero and ignore writes 24 5 3 7 1 System Handler Priority Register 2 The bit...

Page 496: ...does not trigger the SysTick exception logic Reading the register returns its value at the time it is accessed Remark When the processor is halted for debugging the counter does not decrement The sys...

Page 497: ...the current value of the SysTick counter See the register summary in Table 24 451 for its attributes The bit assignments are 24 5 4 4 SysTick Calibration Value Register The SYST_CALIB register indicat...

Page 498: ...ntrol and Status register 24 6 Cortex M0 instruction summary Table 455 SYST_CALIB register bit assignments Bits Name Function 31 NOREF Reads as one Indicates that no separate reference clock is provid...

Page 499: ...LSLS Rd Rm shift 1 Logical shift left by register LSLS Rd Rd Rs 1 Logical shift right by immediate LSRS Rd Rm shift 1 Logical shift right by register LSRS Rd Rd Rs 1 Arithmetic shift right ASRS Rd Rm...

Page 500: ...STM Rn loreglist 1 N 1 Push Push PUSH loreglist 1 N 1 Push with link register PUSH loreglist LR 1 N 1 Pop Pop POP loreglist 1 N 1 Pop and return POP loreglist PC 4 N 2 Branch Conditional B cc label 1...

Page 501: ...ided in this document is subject to legal disclaimers NXP B V 2016 All rights reserved User manual Rev 5 5 21 December 2016 501 of 523 NXP Semiconductors UM10462 Chapter 24 LPC11U3x 2x 1x Appendix ARM...

Page 502: ...ww nxp com documents errata_sheet ES_LPC11U2X pdf 6 LPC11U3x Errata sheet http www nxp com documents errata_sheet ES_LPC11U3X pdf UM10462 Chapter 25 Supplementary information Rev 5 5 21 December 2016...

Page 503: ...ctors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of...

Page 504: ...31 Table 24 System clock control register SYSAHBCLKCTRL address 0x4004 8080 bit description 31 Table 25 SSP0 clock divider register SSP0CLKDIV address 0x4004 8094 bit description 33 Table 26 USART cl...

Page 505: ...dress 0x4004 4000 bit description 86 Table 77 PIO0_1 register PIO0_1 address 0x4004 4004 bit description 87 Table 78 PIO0_2 register PIO0_2 address 0x4004 4008 bit description 88 Table 79 PIO0_3 regis...

Page 506: ...138 Register overview GPIO GROUP0 interrupt base address 0x4005 C000 155 Table 139 Register overview GPIO GROUP1 interrupt base address 0x4006 0000 156 Table 140 Register overview GPIO port base addr...

Page 507: ...COMMON_DESCRIPTOR class structure 176 Table 191 _USB_CORE_DESCS_T class structure 177 Table 192 _USB_DEVICE_QUALIFIER_DESCRIPTOR class structure 177 Table 193 _USB_DFU_FUNC_DESCRIPTOR class structure...

Page 508: ...85 Address Match register RS485ADRMATCH address 0x4000 8050 bit description 267 Table 255 USART RS 485 Delay value register RS485DLY address 0x4000 8054 bit description 268 Table 256 USART Synchronous...

Page 509: ...342 Table 309 Capture register 1 CR1 address 0x4001 0030 CT16B1 bit description 343 Table 310 External Match Register EMR address 0x4000 C03C CT16B0 and 0x4001 003C CT16B1 bit description 343 Table 31...

Page 510: ...tware interaction 399 Table 364 ISP commands allowed for different CRP levels 400 Table 365 ISP command summary 401 Table 366 ISP Unlock command 401 Table 367 ISP Set Baud Rate command 402 Table 368 I...

Page 511: ...ondition code suffixes 460 Table 427 Access instructions 461 Table 428 Data processing instructions 467 Table 429 ADC ADD RSB SBC and SUB operand restrictions 469 Table 430 Branch and control instruct...

Page 512: ...dure 303 Fig 43 Serial clock synchronization 303 Fig 44 Format in the Master Transmitter mode 305 Fig 45 Format of Master Receiver mode 306 Fig 46 A Master Receiver switches to Master Transmitter afte...

Page 513: ...KOUT clock source select register 35 3 5 26 CLKOUT clock source update enable register 35 3 5 27 CLKOUT clock divider register 36 3 5 28 POR captured PIO status register 0 36 3 5 29 POR captured PIO s...

Page 514: ...tup 66 Chapter 6 LPC11U3x 2x 1x NVIC 6 1 How to read this chapter 68 6 2 Introduction 68 6 3 Features 68 6 4 Interrupt sources 68 6 5 Register description 70 6 5 1 Interrupt Set Enable Register 0 regi...

Page 515: ...O group interrupt features 153 9 3 3 GPIO port features 154 9 4 Introduction 154 9 4 1 GPIO pin interrupts 154 9 4 2 GPIO group interrupt 154 9 4 3 GPIO port 154 9 5 Register description 154 9 5 1 GPI...

Page 516: ...SoftConnect 223 11 4 4 Interrupts 224 11 4 5 Suspend and resume 224 11 4 6 Frame toggle output 224 11 4 7 Clocking 225 11 5 Pin description 225 11 6 Register description 225 11 6 1 USB Device Command...

Page 517: ...Data Register 279 13 6 4 SSP SPI Status Register 280 13 6 5 SSP SPI Clock Prescale Register 280 13 6 6 SSP SPI Interrupt Mask Set Clear Register 280 13 6 7 SSP SPI Raw Interrupt Status Register 281 1...

Page 518: ...State 0x40 328 14 11 7 2 State 0x48 328 14 11 7 3 State 0x50 328 14 11 7 4 State 0x58 329 14 11 8 Slave Receiver states 329 14 11 8 1 State 0x60 329 14 11 8 2 State 0x68 329 14 11 8 3 State 0x70 329...

Page 519: ...alue register 381 18 5 4 System Timer Calibration value register SYST_CALIB 0xE000 E01C 382 18 6 Functional description 382 18 7 Example timer calculations 382 Example system clock 50 MHz 382 Chapter...

Page 520: ...IST stop address register 418 20 16 3 EEPROM signature register 419 20 16 4 Flash controller registers 419 20 16 4 1 Flash memory access register 419 20 16 4 2 Flash signature generation 420 20 16 4 3...

Page 521: ...sleep on exit 452 24 3 5 2 2 Wake up from WFE 452 24 3 5 3 Power management programming hints 452 24 4 Instruction set 452 24 4 1 Instruction set summary 452 24 4 2 Intrinsic functions 455 24 4 3 Abou...

Page 522: ...flags 476 24 4 5 9 5 Examples 476 24 4 6 Branch and control instructions 476 24 4 6 1 B BL BX and BLX 476 24 4 6 1 1 Syntax 476 24 4 6 1 2 Operation 477 24 4 6 1 3 Restrictions 477 24 4 6 1 4 Conditio...

Page 523: ...pending Register 487 24 5 2 6 Interrupt Priority Registers 488 24 5 2 7 Level sensitive and pulse interrupts 488 24 5 2 7 1 Hardware and software control of interrupts 489 24 5 2 8 NVIC usage hints a...

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