NXP Semiconductors LPC1102, User Manual

Page: 7 / 258

UM10429 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 1 — 20 October 2010 7 of 258
2.1 How to read this chapter
Table 3 shows the memory configuration for the LPC1102 part.
2.2 Memory map
Figure 2 shows the memory and peripheral address space of the LPC1102.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
On the LPC1102, the GPIO ports are the only AHB peripherals. The APB peripheral area
is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This allows simplifying the address decoding for each
peripheral.
All peripheral register addresses are 32-bit word aligned regardless of their size. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
UM10429
Chapter 2: LPC1102 Memory mapping
Rev. 1 — 20 October 2010 User manual
Table 3. LPC1102 memory configuration
Part Flash SRAM
Suffix
LPC1102 32 kB 8 kB