UM10429
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© NXP B.V. 2010. All rights reserved.
User manual
Rev. 1 — 20 October 2010
21 of 258
NXP Semiconductors
UM10429
Chapter 3: LPC1102 System configuration
3.5.18 WDT clock source update enable register
This register updates the clock source of the watchdog timer with the new input clock after
the WDTCLKSEL register has been written to. In order for the update to take effect at the
input of the watchdog timer, first write a zero to the WDTCLKUEN register and then write
a one to WDTCLKUEN.
Remark:
When switching clock sources, both clocks must be running before the clock
source is updated.
3.5.19 WDT clock divider register
This register determines the divider values for the watchdog clock wdt_clk.
3.5.20 POR captured PIO status register 0
The PIOPORCAP0 register captures the state (HIGH or LOW) of the PIO pins of ports 0,1,
and 2 (pins PIO2_0 to PIO2_7) at power-on-reset. Each bit represents the reset state of
one GPIO pin. This register is a read-only status register.
Table 22.
WDT clock source select register (WDTCLKSEL, address 0x4004 80D0) bit
description
Bit
Symbol
Value
Description
Reset
value
1:0
SEL
WDT clock source
0x00
0x0
IRC oscillator
0x1
Main clock
0x2
Watchdog oscillator
0x3
Reserved
31:2
-
-
Reserved
0x00
Table 23.
WDT clock source update enable register (WDTCLKUEN, address 0x4004 80D4)
bit description
Bit
Symbol
Value
Description
Reset value
0
ENA
Enable WDT clock source update
0x0
0
No change
1
Update clock source
31:1
-
-
Reserved
0x00
Table 24.
WDT clock divider register (WDTCLKDIV, address 0x4004 80D8) bit description
Bit
Symbol
Description
Reset
value
7:0
DIV
WDT clock divider values
0: Disable WDT_PCLK.
1: Divide by 1.
to
255: Divide by 255.
0x00
31:8
-
Reserved
0x00
