NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 205 of 258
NXP Semiconductors
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Chapter 19: Appendix LPC1102 ARM Cortex-M0 reference
STR, STRB and STRH instructions store the word, least-significant byte or lower halfword
contained in the single register specified by
Rt in to memory. The memory address to load
from or store to is the sum of the value in the register specified by either Rn or SP and the
immediate value imm .
19.4.4.2.3 Restrictions
In these instructions:
•
Rt and Rn must only specify R0-R7.
•
imm must be between:
– 0 and 1020 and an integer multiple of four for LDR and STR
using SP as the base register
– 0 and 124 and an integer multiple of four for LDR and STR
using R0-R7 as the base register
– 0 and 62 and an integer multiple of two for LDRH and STRH
– 0 and 31 for LDRB and STRB.
•
The computed address must be divisible by the number of bytes in the transaction,
see
Section 19–19.4.3.4 .
19.4.4.2.4 Condition flags
These instructions do not change the flags.
19.4.4.2.5 Examples
LDR R4, [R7 ; Loads R4 from the address in R7.
STR R2, [R0,#const-struc] ; const-struc is an expression evaluating
; to a constant in the range 0-1020.
19.4.4.3 LDR and STR, register offset
Load and Store with register offset.
19.4.4.3.1 Syntax
LDR Rt , [ Rn , Rm ]
LDR<B|H> Rt , [ Rn , Rm ]
LDR<SB|SH> Rt , [ Rn , Rm ]
STR Rt , [ Rn , Rm ]
STR<B|H> Rt , [ Rn , Rm ]
where:
Rt is the register to load or store.
Rn is the register on which the memory address is based.
Rm is a register containing a value to be used as the offset.