NXP Semiconductors LPC1102, User Manual

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User manual Rev. 1 — 20 October 2010 20 of 258
NXP Semiconductors
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Chapter 3: LPC1102 System configuration
3.5.15 SPI0 clock divider register
This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be
shut down by setting the DIV bits to 0x0.
3.5.16 UART clock divider register
This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can
be shut down by setting the DIV bits to 0x0.
Remark: Note that the UART pins must be configured in the IOCON block before the
UART clock can be enabled.
3.5.17 WDT clock source select register
This register selects the clock source for the watchdog timer. The WDTCLKUEN register
(see
Section 3.5.18 ) must be toggled from LOW to HIGH for the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
16 IOCON Enables clock for I/O configuration block. 0
0 Disable
1 Enable
31:17 - - Reserved 0x00
Table 19. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
…continued
Bit Symbol Value Description Reset
value
Table 20. SPI0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description
Bit Symbol Description Reset
value
7:0 DIV SPI0_PCLK clock divider values
0: Disable SPI0_PCLK.
1: Divide by 1.
to
255: Divide by 255. 0x00
31:8 - Reserved 0x00
Table 21. UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description
Bit Symbol Description Reset
value
7:0 DIV UART_PCLK clock divider values
0: Disable UART_PCLK.
1: Divide by 1.
to
255: Divide by 255. 0x00
31:8 - Reserved 0x00