UM10429
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User manual
Rev. 1 — 20 October 2010
129 of 258
NXP Semiconductors
UM10429
Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
13.8 Example timer operation
shows a timer configured to reset the count and generate an interrupt on match.
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
shows a timer configured to stop and generate an interrupt on match. The
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
13.9 Architecture
The block diagram for 32-bit counter/timer0 and 32-bit counter/timer1 is shown in
.
Fig 26. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
PCLK
prescale
counter
interrupt
timer
counter
timer counter
reset
2
2
2
2
0
0
0
0
1
1
1
1
4
5
6
0
1
Fig 27. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
PCLK
prescale counter
interrupt
timer counter
TCR[0]
(counter enable)
2
2
0
0
1
4
5
6
1
0
