UM10429
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User manual
Rev. 1 — 20 October 2010
120 of 258
NXP Semiconductors
UM10429
Chapter 13: LPC11102 32-bit counter/timers (CT32B0/1)
[1]
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
13.7.1 Interrupt Register (TMR32B0IR and TMR32B1IR)
The Interrupt Register consists of four bits for the match interrupts and one bit for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect.
TMR32B1PC
R/W
0x010
Prescale Counter (PC). The 32-bit PC is a counter which is incremented
to the value stored in PR. When the value in PR is reached, the TC is
incremented and the PC is cleared. The PC is observable and
controllable through the bus interface.
0
TMR32B1MCR
R/W
0x014
Match Control Register (MCR). The MCR is used to control if an
interrupt is generated and if the TC is reset when a Match occurs.
0
TMR32B1MR0
R/W
0x018
Match Register 0 (MR0). MR0 can be enabled through the MCR to reset
the TC, stop both the TC and PC, and/or generate an interrupt every
time MR0 matches the TC.
0
TMR32B1MR1
R/W
0x01C
Match Register 1 (MR1). See MR0 description.
0
TMR32B1MR2
R/W
0x020
Match Register 2 (MR2). See MR0 description.
0
TMR32B1MR3
R/W
0x024
Match Register 3 (MR3). See MR0 description.
0
TMR32B1CCR
R/W
0x028
Capture Control Register (CCR). The CCR controls which edges of the
capture inputs are used to load the Capture Registers and whether or
not an interrupt is generated when a capture takes place.
0
TMR32B1CR0
RO
0x02C
Capture Register 0 (CR0). CR0 is loaded with the value of TC when
there is an event on the CT32B1_CAP0 input.
0
TMR32B1EMR
R/W
0x03C
External Match Register (EMR). The EMR controls the match function
and the external match pins CT32B1_MAT[3:0].
0
-
-
0x040 -
0x06C
reserved
-
TMR32B1CTCR
R/W
0x070
Count Control Register (CTCR). The CTCR selects between Timer and
Counter mode, and in Counter mode selects the signal and edge(s) for
counting.
0
TMR32B1PWMC R/W
0x074
PWM Control Register (PWMCON). The PWMCON enables PWM
mode for the external match pins CT32B1_MAT[3:0].
0
Table 115. Register overview: 32-bit counter/timer 1 CT32B1 (base address 0x4001 8000)
…continued
Name
Access
Address
offset
Description
Reset
value
[1]
Table 116. Interrupt Register (TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000) bit
description
Bit
Symbol
Description
Reset value
0
MR0 Interrupt
Interrupt flag for match channel 0.
0
1
MR1 Interrupt
Interrupt flag for match channel 1.
0
2
MR2 Interrupt
Interrupt flag for match channel 2.
0
3
MR3 Interrupt
Interrupt flag for match channel 3.
0
4
CR0 Interrupt
Interrupt flag for capture channel 0 event.
0
31:5
-
Reserved
-
