UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
846 of 1269
29.1 How to read this chapter
The timers are available on all LPC43xx parts.
29.2 Basic configuration
The Timers are configured as follows:
•
See
for clocking and power control.
•
The Timer0/1/2/3 are reset by the TIMER0/1/2/3_RST (reset #32/33/34/35).
•
The Timer0/1/2/3 interrupts are connected to slot # 12/13/14/15 in the NVIC. Match
channels 2 of Timer0/1/3 are connected to slots # 13, 14, 16 in the Event router.
(These outputs are ORed with SCT outputs 2, 6, 14.)
•
For connecting the match channels 0 and 1 of Timer0/1/2/3 to the GPDMA, use the
DMAMUX register in the CREG block (see
) and enable the GPDMA channel
in the DMA Channel Configuration registers (
).
•
The timer registers can be also accessed by the GPDMA as memory-to-memory
transfer.
•
The timer capture inputs and match outputs are configured through the GIMA (see
).
•
All timer capture inputs are also connected to dedicated external pins (see
and
).
29.3 Features
•
A 32 bit Timer/Counter with a programmable 32 bit Prescaler.
•
Counter or Timer operation
•
Up to four 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
•
Four 32-bit match registers that allow:
UM10503
Chapter 29: LPC43xx Timer0/1/2/3
Rev. 1.3 — 6 July 2012
User manual
Table 677. Timer0/1/2/3 clocking and power control
Base clock
Branch clock
Operating
frequency
Clock to the timer0 register interface and
timer0 peripheral clock PCLK.
BASE_M4_CLK
CLK_M4_TIMER0
up to
204 MHz
Clock to the timer1 register interface and
timer1 peripheral clock PCLK.
BASE_M4_CLK
CLK_M4_TIMER1
up to
204 MHz
Clock to the timer2 register interface and
timer2 peripheral clock PCLK.
BASE_M4_CLK
CLK_M4_TIMER2
up to
204 MHz
Clock to the timer3 register interface and
timer3 peripheral clock PCLK.
BASE_M4_CLK
CLK_M4_TIMER3
up to
204 MHz
