UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
689 of 1269
NXP Semiconductors
UM10503
Chapter 26: LPC43xx Ethernet
Table 536. MAC MII Address register (MAC_MII_ADDR, address 0x4001 0010) bit description
Bit
Symbol
Description
Reset
value
Access
0
GB
MII busy
This register field can be read by the application (Read), can be set to 1 by the
application with a register write of 1 (Write Set), and is cleared to 0 by the core (Self
Clear). The application cannot clear this type of field, and a register write of 0 to this
bit has no effect on this field.
This bit should read a logic 0 before writing to this register and the MAC_MII_DATA
register. This bit must also be set to 0 during a Write to this register. During a PHY
register access, this bit will be set to 1 by the Application to indicate that a Read or
Write access is in progress. The MAC_MII_DATA register should be kept valid until
this bit is cleared by the MAC during a PHY Write operation. The MAC_MII_DATA
register is invalid until this bit is cleared by the MAC during a PHY Read operation.
This register should not be written to until this bit is cleared.
0
R/W
1
W
MII write
When set, this bit tells the PHY that this will be a Write operation using the MII Data
register. If this bit is not set, this will be a Read operation, placing the data in the MII
Data register.
0
R/W
5:2
CR
CSR clock range
The CSR Clock Range selection determines the frequency of the MDC clock. The
suggested range of CLK_M4_ETHERNET frequency applicable for each value below
(when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency
range 1.0 MHz - 2.5 MHz.
When bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE
802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value.
For example, when CLK_M4_ETHERNET is of frequency 100 MHz and you program
these bits as 1010, then the resultant MDC clock will be of 12.5 MHz which is outside
the limit of IEEE 802.3 specified range. Program the values given below only if the
interfacing chips supports faster MDC clocks.
See
for bit values.
0
R/W
10:6
GR
MII register
These bits select the desired MII register in the selected PHY device.
0
R/W
15:11
PA
Physical layer address
This field tells which of the 32 possible PHY devices are being accessed.
0
R/W
31:16
-
Reserved
0
RO
Table 537. CSR clock range values
Bits 5:2
CLK_M4_ETHERNET
MDC clock
0000
60 - 100 MHz
CLK_M4_ETHERNET/42
0001
100 - 150 MHz
CLK_M4_ETHERNET/62
0010
20 - 35 MHz
CLK_M4_ETHERNET/16
0011
35 - 60 MHz
CLK_M4_ETHERNET/26
0100
150 - 250 MHz
CLK_M4_ETHERNET/102
0101
250 - 300 MHz
CLK_M4_ETHERNET/124
0110, 0111
Reserved
-
1000
-
CLK_M4_ETHERNET/42
1001
-
CLK_M4_ETHERNET/62
