NXP Semiconductors LCP43 Series, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 483 of 1269
NXP Semiconductors
UM10503
Chapter 21: LPC43xx External Memory Controller (EMC)
For example, for a static memory read/write transfer time of 16 µs, and a CCLK frequency
of 50 MHz, the following value must be programmed into this register:
(16 x 10
-6
x 50 x 10
6
) / 16 - 1 = 49
21.7.19 Dynamic Memory Configuration registers
The DynamicConfig registers enable you to program the configuration information for the
relevant dynamic memory chip select. These registers are normally only modified during
system initialization. These registers are accessed with one wait state.
[1] The SDRAM column and row width and number of banks are computed automatically from the address
mapping.
[2] The buffers must be disabled during SDRAM initialization. The buffers must be enabled during normal
operation.
Table 372. Dynamic Memory Configuration registers (DYNAMICCONFIG[0:3], address
0x4000 5100 (DYNAMICCONFIG0), 0x4000 5120 (DYNAMICCONFIG1),
0x4000 5140 (DYNAMICCONFIG2), 0x4000 5160 (DYNAMICCONFIG3)) bit
description
Bit Symbol Value Description Reset
value
2:0 - - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -
4:3 MD Memory device. 0
0x0 SDRAM (POR reset value).
0x1 Reserved.
0x2 Reserved.
0x3 Reserved.
6:5 - - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -
12:7 AM0 Address mapping.
See
Table 373 . 000000 = reset value.
[1]
0
13 - - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -
14 AM1 Address mapping
See
Table 373 . 0 = reset value.
0
18:15 - - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -
19 B Buffer enable.
0 Buffer disabled for accesses to this chip select (POR reset
value).
1 Buffer enabled for accesses to this chip select. After
configuration of the dynamic memory, the buffer must be
enabled for normal operation.
[2]
20 P Write protect. 0
0 Writes not protected (POR reset value).
1 Writes protected.
31:21 - - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. -