NXP Semiconductors LCP43 Series, User Manual

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User manual Rev. 1.3 — 6 July 2012 1064 of 1269
NXP Semiconductors
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Chapter 42: LPC43xx C_CAN
42.6 Register description
Register values at reset
After a hardware reset, the registers hold the values described in Table 931 . Additionally,
the busoff state is reset and the output TD0,1 is set to recessive (HIGH). The value
0x0001 (INIT = ‘1’) in the CAN Control Register enables the software initialization. The
CAN controller does not communicate with the CAN bus until the CPU resets INIT to ‘0’.
The data stored in the message RAM is not affected by a hardware reset. After power-on,
the contents of the message RAM is undefined.
Table 931. Register overview: C_CAN0 (base address 0x400E 2000)
Name Access Address
offset Description Reset
value Reference
CNTL R/W 0x000 CAN control register 0x0001 Table 933
STAT R/W 0x004 Status register 0x0000 Table 934
EC RO 0x008 Error counter register 0x0000 Table 935
BT 0x00C Bit timing register 0x2301 Table 936
INT RO 0x010 Interrupt register 0x0000 Table 937
TEST R/W 0x014 Test register - Table 938
BRPE R/W 0x018 Baud rate prescaler extension register 0x0000 Table 939
- - 0x01C Reserved -
IF1_CMDREQ R/W 0x020 Message interface 1 command request 0x0001 Table 942
IF1_CMDMSK_W R/W 0x024 Message interface 1 command mask (write
direction) 0x0000 Table 944
IF1_CMDMSK_R R/W 0x024 Message interface 1 command mask (read
direction) 0x0000 Table 946
IF1_MSK1 R/W 0x028 Message interface 1 mask 1 0xFFFF Table 948
IF1_MSK2 R/W 0x02C Message interface 1 mask 2 0xFFFF Table 950
IF1_ARB1 R/W 0x030 Message interface 1 arbitration 1 0x0000 Table 952
IF1_ARB2 R/W 0x034 Message interface 1 arbitration 2 0x0000 Table 954
IF1_MCTRL R/W 0x038 Message interface 1 message control 0x0000 Table 956
IF1_DA1 R/W 0x03C Message interface 1 data A1 0x0000 Table 958
IF1_DA2 R/W 0x040 Message interface 1 data A2 0x0000 Table 959
IF1_DB1 R/W 0x044 Message interface 1 data B1 0x0000 Table 962
IF1_DB2 R/W 0x048 Message interface 1 data B2 0x0000 Table 964
- 0x04C -
0x07C Reserved -
IF2_CMDREQ R/W 0x080 Message interface 2 command request 0x0001 Table 943
IF2_CMDMSK_W R/W 0x084 Message interface 2 command mask (write
direction) 0x0000 Table 945
IF2_CMDMSK_R R/W 0x084 Message interface 2 command mask (read
direction) 0x0000 Table 947
IF2_MSK1 R/W 0x088 Message interface 2 mask 1 0xFFFF Table 949
IF2_MSK2 R/W 0x08C Message interface 2 mask 2 0xFFFF Table 951
IF2_ARB1 R/W 0x090 Message interface 2 arbitration 1 0x0000 Table 953