UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
1029 of 1269
41.1 How to read this chapter
The I
2
S0/1 interfaces are available on all LPC43xx parts.
41.2 Basic configuration
The I
2
S interface is configured as follows:
•
See
for clocking and power control.
•
The I2S0 is reset by the I2S0_RST (reset # 52).
•
The I2S1 is reset by the I2S1_RST (reset # 53).
•
The I2S0 interrupt is connected to slot # 28 in the NVIC.
•
The I2S1 interrupt is connected to slot # 29 in the NVIC.
•
For connecting the I2S receive and transmit lines to the GPDMA, use the DMAMUX
register in the CREG block (see
) and enable the GPDMA channel in the
DMA Channel Configuration registers (
).
•
See
for configuring the I2S clock inputs for the audio PLL.
•
The I2S0/1 MWS signals
(I2S0_RX_MWS/I2S0_TX_MWS/IS1_RX_MWS/I2S1_TX_MWS) can be connected
to timer3 or the SCT through the GIMA (see
41.3 Features
The I2S bus provides a standard communication interface for digital audio applications.
The I2S bus specification defines a 3-wire serial bus, having one data, one clock, and one
word select signal. The basic I2S connection has one master, which is always the master,
and one slave. The I2S interface provides a separate transmit and receive channel, each
of which can operate as either a master or a slave.
•
The I2S input can operate in both master and slave mode, independently of the I2S
output.
•
The I2S output can operate in both master and slave mode, independently of the I2S
input.
•
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
•
Mono and stereo audio data supported.
•
Versatile clocking includes independent transmit and receive fractional rate
generators, and an ability to use a single clock input or output for a 4-wire mode.
UM10503
Chapter 41: LPC43xx I2S interface
Rev. 1.3 — 6 July 2012
User manual
Table 894. I2S clocking and power control
Base clock
Branch clock
Operating
frequency
Clock to the I2S0 and I2S1 register
interface and I2S0/1 peripheral clock.
BASE_APB1_CLK
CLK_APB1_I2S
up to
204 MHz
