NXP Semiconductors Layerscape LS1028A BSP, User Manual, Page: 66 / 136

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Kernel Configure Tree View Options Description
driver
<*> Freescale CAAM Job Ring driver
backend (SEC)
(9) Job Ring size
[ ] Job Ring interrupt coalescing
<*> Register algorithm
implementations with the Crypto API
<*> Queue Interface as Crypto API
backend
<*> Register hash algorithm
implementations with Crypto API
<*> Register public key
cryptography implementations with Crypto API
<*> Register caam device for
hwrng API
<M> QorIQ DPAA2 CAAM (DPSECI) driver • backends / interfaces:
— Freescale CAAM Job Ring driver backend (SEC) - JRI;
this also enables QI (QI depends on JRI)
— QorIQ DPAA2 CAAM (DPSECI) driver - DPSECI
• frontends / crypto algorithms:
— symmetric encryption, AEAD, "stitched" AEAD, TLS;
Register algorithm implementations with the Crypto API
- via JRI ( caamalg driver) or Queue Interface as Crypto
API backend - via QI ( caamalg_qi drive)
— Register hash algorithm implementations with Crypto
API
- hashing (only via JRI - caamhash driver)
— Register public key cryptography implementations with
Crypto API
- asymmetric / public key (only via JRI -
caam_pkc driver)
— Register caam device for hwrng API - HW RNG (only
via JRI - caamrng driver)
— QorIQ DPAA2 CAAM (DPSECI) driver - DPSECI
• options: debugging, JRI ring size, JRI interrupt coalescing
Networking support --->
Network option --->
<*> TCP/IP networking
<*> IP: AH transformation
<*> IP: ESP transformation
<*> IP: IPsec transport mode
<*> IP: IPsec tunnel mode
For IPsec support the TCP/IP networking option and
corresponding sub-options should be enabled.
Device Tree binding
Property Type Status Description
compatible String Required fsl,sec-vX.Y (preferred) OR
fsl,secX.Y
Sample Device Tree crypto node
crypto@30000 {
compatible = "fsl,sec-v4.0";
fsl,sec-era = <2>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupt-parent = <&mpic>;
interrupts = <92 2>;
clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
Linux kernel
Layerscape LS1028A BSP User Guide, Rev. 0.3, 04/2019
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NXP Semiconductors