NXP Semiconductors Layerscape FRWY-LS1046A Getting Started Manual Download Page 12

NOTICE:  BL2: Built : 12:46:37, Dec 17 2019
NOTICE:  BL31: v1.5(release):LX2160_UEFI_ACPI_EAR1-1-gbf83b558
NOTICE:  BL31: Built : 12:46:42, Dec 17 2019
NOTICE:  Welcome to LS1046 BL31 Phase

U-Boot 2019.10-00007-g0a7a4b0b3f (Dec 17 2019 - 12:45:40 +0800)

SoC:  LS1046AE Rev1.0 (0x87070010)
Clock Configuration:
       CPU0(A72):1600 MHz  CPU1(A72):1600 MHz  CPU2(A72):1600 MHz
       CPU3(A72):1600 MHz
       Bus:      600  MHz  DDR:      2100 MT/s  FMAN:     700  MHz
Reset Configuration Word (RCW):
       00000000: 0c150010 0e000000 00000000 00000000
       00000010: 30400506 00800012 40025000 c1000000
       00000020: 00000000 00000000 00000000 00038800
       00000030: 20044100 24003101 00000096 00000001
Model: LS1046A FRWY Board
Board: LS1046AFRWY, Rev: A, boot from QSPI
SD1_CLK1 = 100.00MHZ, SD1_CLK2 = 100.00MHZ
I2C:   ready
DRAM:  3.9 GiB (DDR4, 64-bit, CL=15, ECC on)
SEC0: RNG instantiated
Using SERDES1 Protocol: 12352 (0x3040)
Using SERDES2 Protocol: 1286 (0x506)
NAND:  512 MiB
MMC:   FSL_SDHC: 0
Loading Environment from SPI Flash... SF: Detected mt25qu512a with page size 256 Bytes, erase 
size 64 KiB, total 64 MiB
OK
EEPROM: NXID v1
In:    serial
Out:   serial
Err:   serial
Net:   SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB
Fman1: Uploading microcode version 106.4.18
PCIe0: pcie@3400000 disabled
PCIe1: pcie@3500000 Root Complex: no link
PCIe2: pcie@3600000 Root Complex: no link
FM1@DTSEC1, FM1@DTSEC5, FM1@DTSEC6, FM1@DTSEC9, FM1@DTSEC10
Error: FM1@DTSEC10 address not set.

Hit any key to stop autoboot:  0
=>

 

The above U-Boot log is an example log; the actual U-Boot log may vary slightly depending on the LSDK version
available on the board.

  NOTE  

 

By default, the FRWY-LS1046A board comes preloaded with LSDK composite firmware image. You can deploy
Ubuntu userland on the board; however, due to limited NOR flash memory (64 MB), you need to use an external
memory device, such as a micro-SD card or USB mass storage device for storing the LSDK images.

For steps to download and assemble updated LSDK images and then to deploy LSDK Ubuntu distribution on the
FRWY-LS1046A board, see "LSDK Quick Start Guide for FRWY-LS1046A" section in 

Layerscape Software

Development Kit User Guide

.

  NOTE  

NXP Semiconductors

Getting started with FRWY-LS1046A

Layerscape FRWY-LS1046A Board Getting Started Guide, Rev. 1, 05/2020

User's Guide

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Summary of Contents for Layerscape FRWY-LS1046A

Page 1: ...pdf Layerscape FRWY LS1046A Board Errata Describes known errata and workarounds for the FRWY LS1046A board Contact FAE sales representative QorIQ LS1046A Product Brief Provides a brief overview of th...

Page 2: ...046A TP FRWY LS1046A AC FRWY LS1046A PA FRWY LS1046A board hardware assembly with enclosure The board comes with the following M 2 cards installed Google Coral TPU module SparkLAN dual band Wi Fi Blue...

Page 3: ...Host connector J55 Micro SD card slot P2 Dual port 1G Ethernet connector P1 Dual port 1G Ethernet connector J56 J57 MikroBUS socket Figure 2 FRWY LS1046A chassis back panel The figure below shows the...

Page 4: ...below shows important jumpers DIP switch and LEDs available on board top view NXP Semiconductors Chassis and board pictures Layerscape FRWY LS1046A Board Getting Started Guide Rev 1 05 2020 User s Gui...

Page 5: ...elow shows the bottom side view of the board with two connectors and one LED highlighted NXP Semiconductors Chassis and board pictures Layerscape FRWY LS1046A Board Getting Started Guide Rev 1 05 2020...

Page 6: ...d attached peripherals The board does not have a power ON OFF switch It is powered ON automatically when connected to external power supply NOTE 6 Connectors Connectors are onboard devices that allow...

Page 7: ...chassis back panel J461 M 2 PCIe connector PCIe x1 M 2 Key E slot 1 Supports a Wi Fi capable Key E 1630 2230 module J52 M 2 PCIe connector PCIe x1 M 2 Key E slot 2 Supports a Wi Fi capable Key E 1630...

Page 8: ...serted default setting J11 1x2 connector PROG_MTR voltage control header NXP use only Open PROG_MTR pin of the processor is powered off default setting Shorted PROG_MTR pin is powered by OVDD 1 8 V J9...

Page 9: ...emory does not contain a valid RCW PBL PLL multipliers in the RCW data are not compatible with the fixed SYSCLK DDRCLK or SDCLK values D4 Green USB1_5V USB1 port of the dual port USB connector J70 is...

Page 10: ...To make the host computer allow a serial connection with the board Download and install appropriate driver based on Windows version on the host computer from the following link https www silabs com pr...

Page 11: ...ion between the board and the host computer 7 Optionally connect an Ethernet cable if you want to connect your board to the network for example for obtaining latest board software and updating board i...

Page 12: ...106 4 18 PCIe0 pcie 3400000 disabled PCIe1 pcie 3500000 Root Complex no link PCIe2 pcie 3600000 Root Complex no link FM1 DTSEC1 FM1 DTSEC5 FM1 DTSEC6 FM1 DTSEC9 FM1 DTSEC10 Error FM1 DTSEC10 address n...

Page 13: ...memory may be corrupt In this case use CodeWarrior TAP to flash new images and recover the board For details see CodeWarrior TAP Probe User Guide 12 Revision history The table below summarizes revisio...

Page 14: ...TermsandConditions While NXP has implemented advanced security features all products may be subject to unidentified vulnerabilities Customers are responsible for the design and operation of their appl...

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