NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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39.4.27 FTM PWM Load (FTMx_PWMLOAD)
Enables the reload of the MOD, HCR, CNTIN, C(n)V, and C(n+1)V registers with the
values of their write buffers when the FTM counter changes from the MOD register value
to its next value or when a channel (j) match occurs. A match occurs for channel (j) when
FTM counter = C(j)V. A reload can also occurs when FTM counter = HCR register at a
half cycle match. This register also controls the local and global load mechanisms.
Address: Base a 98h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
GLEN LDOK
HCSEL
CH7SEL CH6SEL CH5SEL CH4SEL CH3SEL CH2SEL CH1SEL CH0SEL
W
GLDOK
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_PWMLOAD field descriptions
Field Description
31–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11
GLDOK
Global Load OK
This bit controls the global load mechanism. It generates a pulse at FTM module global load output with
one FTM clock cycle width, which is used to set LDOK bits of FTM and other modules (including other
FTMs). This bit is self-cleared and read value is always zero.
The global load mechanism depends on SoC specific information. Refer to FTM SoC specific information
to more details.
0 No action.
1 LDOK bit is set.
Table continues on the next page...
Memory map and register definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
906 NXP Semiconductors