NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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39.3 FTM signal descriptions
Table 39-2 shows the user-accessible signals for the FTM.
Table 39-2. FTM signal descriptions
Signal Description I/O Function
EXTCLK External clock. FTM external
clock can be selected to drive
the FTM counter. I The external clock input signal is used as the FTM counter
clock if selected by CLKS[1:0] bits in the SC register. This
clock signal must not exceed 1/4 of FTM input clock
frequency. The FTM counter prescaler selection and settings
are also used when an external clock is selected.
CHn FTM channel (n), where n can
be 7-0 I/O Each FTM channel can be configured to operate either as
input or output. The direction associated with each channel,
input or output, is selected according to the mode assigned
for that channel.
FAULTj Fault input (j), where j can be
3-0 I The fault input signals are used to control the CHn channel
output state. If a fault is detected, the FAULTj signal is
asserted and the channel output is put in a safe state. The
behavior of the fault logic is defined by the FAULTM[1:0]
control bits in the MODE register and FAULTEN bit in the
COMBINE register. Note that each FAULTj input may affect
all channels selectively since FAULTM[1:0] and FAULTEN
control bits are defined for each pair of channels. Because
there are several FAULTj inputs, maximum of 4 for the FTM
module, each one of these inputs is activated by the
FAULTjEN bit in the FLTCTRL register.
PHA Quadrature decoder phase A
input. Input pin associated
with quadrature decoder
phase A. I The quadrature decoder phase A input is used as the
Quadrature Decoder mode is selected. The phase A input
signal is one of the signals that control the FTM counter
increment or decrement in the Quadrature Decoder mode .
PHB Quadrature decoder phase B
input. Input pin associated
with quadrature decoder
phase B. I The quadrature decoder phase B input is used as the
Quadrature Decoder mode is selected. The phase B input
signal is one of the signals that control the FTM counter
increment or decrement in the Quadrature Decoder mode .
39.4 Memory map and register definition
39.4.1 Memory map
This section presents a high-level summary of the FTM registers and how they are
mapped.
The registers and bits of an unavailable function in the FTM remain in the memory map
and in the reset value, but they have no active function.
Chapter 39 FlexTimer Module (FTM)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 855