NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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36.5 Functional description
The ADC module is disabled during reset, or when SC1n[ADCH] are all high; see the
power management information for details. The module is idle when a conversion has
completed and another conversion has not been initiated. When it is idle the module is in
its lowest power state. The ADC can perform an analog-to-digital conversion on any of
the software selectable channels. All modes perform conversion by a successive
approximation algorithm.
To meet accuracy specifications, the ADC module must be calibrated using the on-chip
calibration function.
See Calibration function for details on how to perform calibration.
When the conversion is completed, the result is placed in the Rn data registers. The
respective SC1n[COCO] is then set and an interrupt is generated if the respective
conversion complete interrupt has been enabled, or when SC1n[AIEN]=1.
The ADC module has the capability of automatically comparing the result of a
conversion with the contents of the CV1 and CV2 registers. The compare function is
enabled by setting SC2[ACFE] and operates in any of the conversion modes and
configurations.
The ADC module has the capability of automatically averaging the result of multiple
conversions. The hardware average function is enabled by setting SC3[AVGE] and
operates in any of the conversion modes and configurations.
NOTE
For the chip-specific modes of operation, see the power
management information of this MCU.
36.5.1 Clock select and divide control
One of four clock sources can be selected as the clock source for the ADC module.
This clock source is then divided by a configurable value to generate the input clock
ADCK, to the module. The clock is selected from one of the following sources by means
of CFG1[ADICLK].
Chapter 36 Analog-to-Digital Converter (ADC)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 763