NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 746 / 1325

ADCx_CFG1 field descriptions (continued)
Field Description
8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–5
ADIV
Clock Divide Select
Selects the divide ratio used by the ADC to generate the internal clock ADCK.
00 The divide ratio is 1 and the clock rate is input clock.
01 The divide ratio is 2 and the clock rate is (input clock)/2.
10 The divide ratio is 4 and the clock rate is (input clock)/4.
11 The divide ratio is 8 and the clock rate is (input clock)/8.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–2
MODE
Conversion mode selection
Selects the ADC resolution.
00 8-bit conversion.
01 12-bit conversion.
10 10-bit conversion.
11 Reserved
ADICLK Input Clock Select
Selects the input clock source to generate the internal clock, ADCK. See the clock distribution/clocking
chapter of your device for details on which alternate clocks are supported.
00 Alternate clock 1 (ADC_ALTCLK1)
01 Alternate clock 2 (ADC_ALTCLK2)
10 Alternate clock 3 (ADC_ALTCLK3)
11 Alternate clock 4 (ADC_ALTCLK4)
36.4.3 ADC Configuration Register 2 (ADCx_CFG2)
Configuration Register 2 (CFG2) selects the long sample time duration during long
sample mode.
NOTE
Writing 0 is not supported on this register.
Address: Base a 44h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SMPLTS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
Memory map and register definitions
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
746 NXP Semiconductors