NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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Table 31-4. MDM-AP Control register assignments (continued)
Bit Name Secure
1
Description
1 Suspend operation—hold the core in reset at the end of reset
sequencing. Once the system enters this suspended state, clearing
this control bit immediately releases the core from reset and CPU
operation begins.
5– 31 Reserved for future use N
1. Command available in secure mode
2. DHCSR: refer to the Debug Halting Control and Status Register in the ARMv6-M Architecture Reference Mannual.
31.4 Debug resets
The debug system receives the following sources of reset:
• System POR reset
Conversely, the debug system is capable of generating system reset using the following
mechanism:
• A system reset in the DAP control register which allows the debugger to hold the
system in reset.
• Writing 1 to the SYSRESETREQ field in the NVIC Application Interrupt and Reset
Control register
• A system reset in the DAP control register which allows the debugger to hold the
core in reset.
31.5 Micro Trace Buffer (MTB)
The Micro Trace Buffer (MTB) provides a simple execution trace capability for the
Cortex-M0+ processor. When enabled, the MTB records changes in program flow
reported by the Cortex-M0+ processor, via the execution trace interface, into a
configurable region of the SRAM. Subsequently an off-chip debugger may extract the
trace information, which would allow reconstruction of an instruction flow trace. The
MTB does not include any form of load/store data trace capability or tracing of any other
information.
In addition to providing the trace capability, the MTB also operates as a simple AHB-Lite
SRAM controller. The system bus masters, including the processor, have read/write
access to all of the SRAM via the AHB-Lite interface, allowing the memory to also be
used to store program and data information. The MTB simultaneously stores the trace
Chapter 31 Debug
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 639