NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 582 / 1325

26.4.1 Full Performance Mode (FPM)
For the following Chip Power Modes, the internal voltage regulator is in full performance
mode: HSRUN, RUN, WAIT.
26.4.2 Low Power Mode (LPM)
For the following Chip Power Modes, the internal voltage regulator is in low power
mode: STOP, VLPR, VLPW, VLPS.
26.5 Low Voltage Detect (LVD) System
NOTE
The low voltage detect system (Low voltage detect flag, Low
voltage warning flag and Low voltage detect reset generation)
is disabled in low power mode.
This device includes a system to guard against low voltage conditions. This protects
memory contents and controls MCU system states during supply voltage variations. The
system is comprised of a power-on reset (POR) circuit and a LVD circuit with two trip
points. The LVD is disabled upon entering low power mode.
Two flags are available to indicate the status of the low voltage detect system:
• The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF
bit is set when the supply voltage falls below the trip point (V
LVD
). The LVDF bit is
cleared by writing one to the LVDACK bit, but only if the internal supply has
returned above the trip point; otherwise, the LVDF bit remains set.
• The low voltage warning flag (LVWF) operates in a level sensitive manner. The
LVWF bit is set when the supply voltage falls below the selected monitor trip point
(V
LVW
). The LVWF bit is cleared by writing one to the LVWACK bit, but only if the
internal supply has returned above the trip point; otherwise, the LVWF bit remains
set.
26.5.1 Low Voltage Reset (LVR) Operation
If the supply voltage falls below the reset trip point (V
LVR
), a system reset will be
generated.
If PMC_LVDSC1[LVDRE] is set and the supply voltage falls below V
LVD
, a system
reset will be generated.
Low Voltage Detect (LVD) System
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
582 NXP Semiconductors