NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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SCG_LPFLLDIV field descriptions (continued)
Field Description
10–8
LPFLLDIV2
LPFLL Clock Divide 2
Clock divider 2 for the LPFLL. Used by modules that need an asynchronous clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
7–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
LPFLLDIV1 LPFLL Clock Divide 1
Clock divider 1 for LPFLL. Used to generate the clock source for modules that need an asynchronous
clock source.
000 Output disabled
001 Divide by 1
010 Divide by 2
011 Divide by 4
100 Divide by 8
101 Divide by 16
110 Divide by 32
111 Divide by 64
18.3.20 Low Power FLL Configuration Register (SCG_LPFLLCFG)
The LPFLLCFG register cannot be changed when the LPFLL is enabled. When the
LPFLL is enabled, writes to this register are ignored, and there is no transfer error.
Address: 4006_4000h base + 508h offset = 4006_4508h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FSEL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_LPFLLCFG field descriptions
Field Description
31–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
FSEL Frequency Select
Table continues on the next page...
Chapter 18 System Clock Generator (SCG)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 399