NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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SCG_LPFLLCSR field descriptions
Field Description
31–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
LPFLLERR
LPFLL Clock Error
This flag is reset on Chip POR only, software can also clear this flag by writing a logic one
When LPFLLTREN=1 and LPFLLTRUP=1, LPFLLERR=1 if the LPFLL can’t lock the reference clock. This
occurs when the reference clock is too fast/slow or LPFLL clock is stopped. LPFLLERR indicates a loss of
lock or loss of clock.
To change the reference clock frequency to re-lock, the LPFLLTREN or LPFLLTRUP bits must also be re-
enabled (LPFLLTREN=1 or LPFLLTRUP=1).
0 Error not detected with the LPFLL trimming.
1 Error detected with the LPFLL trimming.
25
LPFLLSEL
LPFLL Selected
0 LPFLL is not the system clock source
1 LPFLL is the system clock source
24
LPFLLVLD
LPFLL Valid
0 LPFLL is not enabled or clock is not valid.
1 LPFLL is enabled and output clock is valid.
23
LK
Lock Register
This bit field can be cleared/set at any time.
0 Control Status Register can be written.
1 Control Status Register cannot be written.
22–18
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
17
LPFLLCMRE
LPFLL Clock Monitor Reset Enable
0 Clock Monitor generates interrupt when error detected
1 Clock Monitor generates reset when error detected
16
LPFLLCM
LPFLL Clock Monitor
Enables the clock monitor when LPFLLTREN is set and LPFLL is enabled. The clock monitor is always
disabled in low power modes. When the clock monitor is disabled in a low power mode, it remains
disabled until the clock valid flag is set following exit from the low power mode.
0 LPFLL Clock Monitor is disabled
1 LPFLL Clock Monitor is enabled
15–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10
LPFLLTRMLOCK
LPFLL Trim LOCK
Asserts only when LPFLLTREN=1 and LPFLLTRUP=1 and LPFLL has locked to target frequency.
1
0 LPFLL not Locked
1 LPFLL trimmed and Locked
Table continues on the next page...
Chapter 18 System Clock Generator (SCG)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 397