NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 272 / 1325

Table 14-1. System memory map (continued)
System 32-bit Address Range Destination Slave Access
0xF800_0000–0xFFFF_FFFF IOPORT: RGPIO (single cycle) Cortex-M0+ core
only
1. This map provides the complete architectural address space definition for the flash. Based on the physical sizes of the
memories implemented for a particular device, the actual address regions used may be smaller. See Flash Memory Sizes
for details.
2. This range varies depending on amount of SRAM implemented for a particular device. See SRAM sizes for details.
NOTE
1. Access rights to AIPS-Lite peripheral bridge and general
purpose input/output (GPIO) module address space is
limited to the core, DMA.
2. The SRAM on this device could be accessed through
normal way with 32-bit operation, and also could be
accessed with bit operation through aliased bit-band region.
14.4.1 Aliased bit-band regions
The device supports aliased SRAM_U bit-band region with Cortex M0+ core. A 32-bit
write in the alias region has the same result as a read-modify-write operation on the
targeted bit in the bit-band region, but with only one cycle time. Aliased bit-band region
is much more efficient for bit operation.
Bit 0 of the value written to the alias region determines what value is written to the target
bit:
• Writing a value with bit 0 set writes a 1 to the target bit.
• Writing a value with bit 0 clear writes a 0 to the target bit.
A 32-bit read in the alias region returns either:
• a value of 0x0000_0000 to indicate the target bit is clear
• a value of 0x0000_0001 to indicate the target bit is set
System memory map
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
272 NXP Semiconductors