NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 143 / 1325

11.4.1.2 TRGMUX_CTRL0 (TRGMUX_CTRL0)
11.4.1.2.1 Address
Register Offset
TRGMUX_CTRL0 40063000h
11.4.1.2.2 Function
TRGMUX Register
11.4.1.2.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R LK
Rese
rved
SEL3 Reserved SEL2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved SEL1 Reserved SEL0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
11.4.1.2.4 Fields
Field Function
31
LK
Enable
This bit shows whether the register can be written or not.
0 - Register can be written.
1 - Register cannot be written until the next system Reset.
30
—
This read-only bit field is reserved and always has the value 0.
29-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. Refer to the
Select Bit Fields table in the Features section for bit field information.
23-22
—
This read-only bit field is reserved and always has the value 0.
21-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. Refer to the
Select Bit Fields table in the Features section for bit field information.
Table continues on the next page...
Chapter 11 Trigger MUX Control (TRGMUX)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 143