NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1196 / 1325

Field Function
NOTE: In case the LPUART is programmed with ILT = 1, a logic 0 is automatically shifted after a
received stop bit, therefore resetting the idle count.
0 - Idle character bit count starts after start bit.
1 - Idle character bit count starts after stop bit.
1
PE
Parity Enable
Enables hardware parity generation and checking. When parity is enabled, the bit immediately before the
stop bit is treated as the parity bit.
0 - No hardware parity generation or checking.
1 - Parity enabled.
0
PT
Parity Type
Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number
of 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the
data character, including the parity bit, is even.
0 - Even parity.
1 - Odd parity.
46.3.1.9 LPUART Data (DATA)
46.3.1.9.1 Address
Register Offset
DATA Base a 1Ch offset
46.3.1.9.2 Function
This register is actually two separate registers. Reads return the contents of the read-only
receive data buffer and writes go to the write-only transmit data buffer. Reads and writes
of this register are also involved in the automatic flag clearing mechanisms for some of
the LPUART status flags.
Register definition
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1196 NXP Semiconductors