NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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LPI2Cx_SRDR field descriptions (continued)
Field Description
14
RXEMPTY
RX Empty
0 The Receive Data Register is not empty.
1 The Receive Data Register is empty.
13–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
DATA Receive Data
Reading this register returns the data received by the I2C slave.
45.4 Functional description
45.4.1 Clocking and Resets
45.4.1.1 Functional clock
The LPI2C functional clock is asynchronous to the bus clock and can remain enabled in
low power modes to support I2C bus transfers by the LPI2C master. It is also used by the
LPI2C slave to support digital filter and data hold time configurations. The LPI2C master
divides the functional clock by a prescaler and the resulting frequency must be at least
eight times faster than the I2C bus bandwidth.
45.4.1.2 External clock
The LPI2C slave logic is clocked directly from the external pins LPI2C_SCL and
LPI2C_SDA (or LPI2C_SCLS and LPI2C_SDAS if master and slave are implemented
on separate pins). This allows the LPI2C slave to remain operational, even when the
LPI2C functional clock is disabled. Note that the LPI2C slave digital filter must be
disabled if the LPI2C functional clock is disabled and this can effect compliance with
some of the timing parameters of the I2C specification, such as the data hold time.
Chapter 45 Low Power Inter-Integrated Circuit (LPI2C)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1161