NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1114 / 1325

44.4.1.3 Bus clock
The bus clock is only used for bus accesses to the control and configuration registers. The
bus clock frequency must be sufficient to support the data bandwidth requirements of the
LPSPI registers, including FIFOs.
44.4.1.4 Chip reset
The logic and registers for the LPSPI are reset to their default state on a chip reset.
44.4.1.5 Software reset
The LPSPI implements a software reset bit in the Control Register. The MCR[RST] will
reset all logic and registers to their default state, except for the MCR itself.
44.4.1.6 FIFO reset
The LPSPI implements write-only control bits that resets the transmit/command FIFO
(MCR[RTF] and receive FIFO (MCR[RRF]). A FIFO is empty after being reset.
44.4.2 Master Mode
44.4.2.1 Transmit and Command FIFO
The transmit and command FIFO is a combined FIFO that includes both transmit data
and command words. Command words are stored to the transmit/command FIFO by
writing the transmit command register. Transmit data words are stored to the transmit/
command FIFO by writing the transmit data register.
When a command word is at the top of the transmit/command FIFO, the following
actions can occur:
• If the LPSPI is between frames, the command word is pulled from the FIFO and
controls all subsequent transfers.
• If the LPSPI is busy and either the existing CONT bit is clear or the new CONTC
value is clear, the SPI frame will complete at the end of the existing word, ignoring
Functional description
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
1114 NXP Semiconductors