NXP Semiconductors Kinetis KE1xZ256, Reference Manual

Page: 1113 / 1325

44.3.17 Receive Data Register (LPSPIx_RDR)
Address: Base a 74h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPSPIx_RDR field descriptions
Field Description
DATA Receive Data
44.4 Functional description
44.4.1 Clocking and Resets
44.4.1.1 Functional clock
The LPSPI functional clock is asynchronous to the bus clock and can remain enabled in
low power modes to support SPI bus transfers in both master and slave modes. If the
functional clock is disabled in slave mode, the LPSPI can transfer a single word before
the functional clock needs to be enabled. The LPSPI divides the functional clock by a
prescaler and the resulting frequency must be at least two times faster than the SPI clock
frequency.
44.4.1.2 External clock
The LPSPI shift register is clocked directly by the external pins. This allows the LPISPI
slave to remain operational in low power modes, even when the LPSPI functional clock
is disabled, although this is limited to a single word transfer.
Chapter 44 Low Power Serial Peripheral Interface (LPSPI)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1113