NXP Semiconductors Kinetis KE1xZ256, Reference Manual

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• Set timer period for channel 0 as 1 second;
• Enable channel0 interrupt;
• Starts the timer counting afer all configuration;
• In the channel interrupt rountine, clear the channel flag every 1 second.
The following pseudo-code matches the described setup above:
CLOCK_EnableClock(LPIT0);
LPIT0_MCR |= LPIT_MCR_SW_RST_MASK;
LPIT0_MCR &= ~LPIT_MCR_SW_RST_MASK;
LPIT0_MCR |= (LPIT_MCR_DBG_EN(1) | LPIT_MCR_DOZE_EN(1) | LPIT_MCR_M_CEN_MASK);
LPIT0_TCTRL0 |= LPIT_TCTRL_MODE(0);
LPIT0_TVAL0 = ONE_SECOND_VALUE;
LPIT0_MIER |= LPIT_MIER_TIE0_MASK;
NVIC_EnableIRQ(LPIT0_IRQ);
LPIT0_SETTEN |= LPIT_SETTEN_SET_T_EN_0_MASK;
40.6.2 LPIT/ADC Trigger
The LPIT could be used as an alternate ADC hardware trigger source, whose
implementation is via TRGMUX. Each LPIT channel supports one pre-trigger and one
trigger. The LPIT channels are implemented based on independent counters. When used
as ADC trigger source, the channel outputs are ORed together to generate the ADC
hardware trigger. The following diagram shows an example of using LPIT triggering
ADC0.
Chapter 40 Low-power Periodic Interrupt Timer (LPIT)
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 1027