NXP Semiconductors KE1xF Series, Reference Manual, Page: 990 / 1483

41.4.13 Output Mask (FTMx_OUTMASK)
This register provides a mask for each FTM channel. The mask of a channel determines if
its output responds, that is, it is masked or not, when a match occurs. This feature is used
for BLDC control where the PWM signal is presented to an electric motor at specific
times to provide electronic commutation.
Any write to the OUTMASK register, stores the value in its write buffer. The register is
updated with the value of its write buffer according to
PWM synchronization .
Output Mask bits must not be set for trigger mode.
Address: Base a 60h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CH7OM CH6OM CH5OM CH4OM CH3OM CH2OM CH1OM CH0OM
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_OUTMASK field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
CH7OM
Channel 7 Output Mask
Defines if the channel output is masked or unmasked.
0 Channel output is not masked. It continues to operate normally.
1 Channel output is masked. It is forced to its inactive state.
6
CH6OM
Channel 6 Output Mask
Defines if the channel output is masked or unmasked.
0 Channel output is not masked. It continues to operate normally.
1 Channel output is masked. It is forced to its inactive state.
5
CH5OM
Channel 5 Output Mask
Defines if the channel output is masked or unmasked.
Table continues on the next page...
Memory map and register definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
990 NXP Semiconductors