NXP Semiconductors KE1xF Series, Reference Manual, Page: 94 / 1483

6.2.5 Store Buffer Fault address register (MCM_FADR)
When a properly-enabled cache write buffer error interrupt event is detected, the faulting
address is captured in the MCM_FADR register. The MCM logic supports capturing a
single cache write buffer bus error event; if a subsequent error is detected before the
captured error information has been read from the corresponding registers and the
MCM_ISCR[CWBER] indicator cleared, the MCM_FATR[BEOVR] flag is set.
However, no additional information is captured.
The bits in this register are set by hardware and signaled by the assertion of
MCM_ISCR[CWBER]. Attempted writes have no effect.
Address: E008_0000h base + 20h offset = E008_0020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ADDRESS
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
MCM_FADR field descriptions
Field Description
ADDRESS Fault address
6.2.6 Store Buffer Fault Attributes register (MCM_FATR)
When a properly-enabled cache write buffer error interrupt event is detected, the faulting
attributes are captured in the MCM_FATR register.
The bits in this register are set by hardware and signaled by the assertion of
MCM_ISCR[CWBER]. Attempted writes have no effect.
Memory map/register descriptions
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
94 NXP Semiconductors