NXP Semiconductors KE1xF Series, Reference Manual, Page: 890 / 1483

CMPx_C0 field descriptions (continued)
Field Description
NOTE:
• If OFFSET = 1, then there will be no hysteresis in the case of INP crossing INN in the
positive direction (or INN crossing INP in the negative direction). A Half Hysteresis value
still exists for INP crossing INN in the falling direction.
• If OFFSET = 0, then the hysteresis selected by HYSTCTR is valid for both directions.
0 The comparator hard block output has level 0 offset internally.
1 The comparator hard block output has level 1 offset internally.
HYSTCTR Comparator hard block hysteresis control. See chip data sheet to get the actual hysteresis value with each
level
00 The hard block output has level 0 hysteresis internally.
01 The hard block output has level 1 hysteresis internally.
10 The hard block output has level 2 hysteresis internally.
11 The hard block output has level 3 hysteresis internally.
38.8.2 CMP Control Register 1 (CMPx_C1)
Access:
• Supervisor read/write
• User read/write
Address: Base a 4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 0
INPSEL
0
INNSEL
CHN7 CHN6 CHN5 CHN4 CHN3 CHN2 CHN1 CHN0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DACEN
VRSEL
PSEL MSEL VOSEL
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CMPx_C1 field descriptions
Field Description
31–30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map/register definitions
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
890 NXP Semiconductors