NXP Semiconductors KE1xF Series, Reference Manual, Page: 89 / 1483

6.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)
PLAMC is a 16-bit read-only register identifying the presence/absence of bus master
connections to the device's crossbar switch.
Address: E008_0000h base + Ah offset = E008_000Ah
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 AMC
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
MCM_PLAMC field descriptions
Field Description
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input
port.
0 A bus master connection to AXBS input port n is absent
1 A bus master connection to AXBS input port n is present
6.2.3 Core Platform Control Register (MCM_CPCR)
Control Register defines the arbitration and protection schemes for the two system RAM
arrays.
NOTE
Bits 23-0 are undefined after reset.
Address: E008_0000h base + Ch offset = E008_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
SRAMLWP
SRAMLAP
0
SRAMUWP
SRAMUAP Reserved
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 6 Miscellaneous Control Module (MCM)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 89