NXP Semiconductors KE1xF Series, Reference Manual, Page: 834 / 1483

The following table describes the behavior of the data result registers in the different
modes of operation.
Table 37-6. Data result register description
Conversion mode D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Format
12-bit single-ended D Unsigned right-
justified
10-bit single-ended 0 D
8-bit single-ended 0 D
D: Data. The data result registers are read-only; writing to these registers generates a
transfer error.
Address: Base a 48h (4d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 D
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCx_Rn field descriptions
Field Description
31–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
D Data result
37.4.5 Compare Value Registers (ADCx_CVn)
The Compare Value Registers (CV1 and CV2) contain a compare value used to compare
the conversion result when the compare function is enabled, that is, SC2[ACFE]=1. This
register is formatted in the same way as the Rn registers. Therefore, the compare function
uses only the CVn fields that are related to the ADC mode of operation.
CV2 is used only when the compare range function is enabled, that is, SC2[ACREN]=1.
Address: Base a 88h (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CV
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register definitions
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
834 NXP Semiconductors