NXP Semiconductors KE1xF Series, Reference Manual, Page: 1449 / 1483

Because the user is not able to synchronize the CODE field update with the FlexCAN
internal processes, an inactivation can have the following consequences:
• A frame in the bus that matches the filtering of the inactivated Rx Mailbox may be
lost without notice, even if there are other Mailboxes with the same filter
• A frame containing the message within the inactivated Tx Mailbox may be
transmitted without setting the respective IFLAG
In order to perform a safe inactivation and avoid the above consequences for Tx
Mailboxes, the CPU must use the Transmission Abort mechanism (see
Transmission
abort mechanism ).
The inactivation automatically unlocks the Mailbox (see Mailbox lock mechanism ).
NOTE
Message Buffers that are part of the Rx FIFO cannot be
inactivated. There is no write protection on the FIFO region by
FlexCAN. CPU must maintain data coherency in the FIFO
region when RFEN is asserted.
50.5.6.3 Mailbox lock mechanism
Other than Mailbox inactivation, FlexCAN has another data coherence mechanism for the
receive process. When the CPU reads the Control and Status word of an Rx MB with
codes FULL or OVERRUN, FlexCAN assumes that the CPU wants to read the whole
MB in an atomic operation, and therefore it sets an internal lock flag for that MB. The
lock is released when the CPU reads the Free Running Timer (global unlock operation),
or when it reads the Control and Status word of another MB regardless of its code. A
CPU write into the C/S word also unlocks the MB, but this procedure is not
recommended for normal unlock use because it cancels a pending-move and potentially
may lose a received message. The MB locking prevents a new frame from being written
into the MB while the CPU is reading it.
NOTE
The locking mechanism applies only to Rx MBs that are not
part of the FIFO and have a code different than INACTIVE
(0b0000) or EMPTY
1
(0b0100). Also, Tx MBs can not be
locked.
1. In previous FlexCAN versions, reading the C/S word locked the MB even if it was
EMPTY. This behavior is maintained when the IRMQ bit is negated.
Chapter 50 CAN (FlexCAN)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1449