NXP Semiconductors KE1xF Series, Reference Manual, Page: 1423 / 1483

50.4.17 CAN Bit Timing Register (CANx_CBT)
This register is an alternative way to store the CAN bit timing variables described in
CAN_CTRL1 register. EPRESDIV, EPROPSEG, EPSEG1, EPSEG2 and ERJW are
extended versions of PRESDIV, PROPSEG, PSEG1, PSEG2 and RJW bit fields
respectively.
The BTF bit selects the use of the timing variables defined in this register.
The contents of this register are not affected by soft reset.
NOTE
The CAN bit variables in CAN_CTRL1 and in CAN_CBT are
stored in the same register.
NOTE
The user must ensure bit time settings and protocol engine
tolerance are in compliance with the CAN Protocol standard
(ISO 11898-1).
Address: Base a 50h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BTF EPRESDIV ERJW
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EPROPSEG EPSEG1 EPSEG2
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_CBT field descriptions
Field Description
31
BTF
Bit Timing Format Enable
Enables the use of extended CAN bit timing fields EPRESDIV, EPROPSEG, EPSEG1, EPSEG2 and
ERJW replacing the CAN bit timing variables defined in CAN_CTRL1 register. This field can be written in
Freeze mode only.
0 Extended bit time definitions disabled.
1 Extended bit time definitions enabled.
30–21
EPRESDIV
Extended Prescaler Division Factor
This 10-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency
when CAN_CBT[BTF] bit is asserted, otherwise it has no effect. It extends the CAN_CTRL1[PRESDIV]
value range.
The Sclock period defines the time quantum of the CAN protocol. For the reset value, the Sclock
frequency is equal to the PE clock frequency (see
Protocol timing ). This field can be written only in Freeze
mode because it is blocked by hardware in other modes.
Table continues on the next page...
Chapter 50 CAN (FlexCAN)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1423