NXP Semiconductors KE1xF Series, Reference Manual, Page: 1419 / 1483

50.4.13 Error and Status 2 register (CANx_ESR2)
This register reports some general status information.
Address: Base a 38h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 LPTM
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 VPS IMB 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CANx_ESR2 field descriptions
Field Description
31–23
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
22–16
LPTM
Lowest Priority Tx Mailbox
If CAN_ESR2[VPS] is asserted, this field indicates the lowest number inactive Mailbox (see the
CAN_ESR2[IMB] bit description). If there is no inactive Mailbox then the Mailbox indicated depends on
CAN_CTRL1[LBUF] bit value. If CAN_CTRL1[LBUF] bit is negated then the Mailbox indicated is the one
that has the greatest arbitration value (see the "Highest priority Mailbox first" section). If
CAN_CTRL1[LBUF] bit is asserted then the Mailbox indicated is the highest number active Tx Mailbox. If a
Tx Mailbox is being transmitted it is not considered in LPTM calculation. If CAN_ESR2[IMB] is not
asserted and a frame is transmitted successfully, LPTM is updated with its Mailbox number.
15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
14
VPS
Valid Priority Status
This bit indicates whether CAN_ESR2[IMB] and CAN_ESR2[LPTM] contents are currently valid or not. It is
asserted upon every complete Tx arbitration process unless the CPU writes to Control and Status word of
a Mailbox that has already been scanned, that is, it is behind Tx Arbitration Pointer, during the Tx
arbitration process. If there is no inactive Mailbox and only one Tx Mailbox that is being transmitted then
VPS is not asserted. This bit is negated upon the start of every Tx arbitration process or upon a write to
Control and Status word of any Mailbox.
NOTE: CAN_ESR2[VPS] is not affected by any CPU write into Control Status (C/S) of a MB that is
blocked by abort mechanism. When CAN_MCR[AEN] is asserted, the abort code write in C/S of a
MB that is being transmitted (pending abort), or any write attempt into a Tx MB with CAN_IFLAG
set is blocked.
0 Contents of IMB and LPTM are invalid.
1 Contents of IMB and LPTM are valid.
13
IMB
Inactive Mailbox
If ESR2[VPS] is asserted, this bit indicates whether there is any inactive Mailbox (CODE field is either
0b1000 or 0b0000). This bit is asserted in the following cases:
Table continues on the next page...
Chapter 50 CAN (FlexCAN)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1419