NXP Semiconductors KE1xF Series, Reference Manual, Page: 1135 / 1483

42.4.10 Timer Control Register (LPITx_TCTRLn)
These registers contain the control bits for each timer channel
Address: 4003_7000h base + 28h (16d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
TRG_SEL
TRG_
SRC
0
TROT TSOI TSOT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MODE
CHAIN
T_EN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPITx_TCTRLn field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
TRG_SEL
Trigger Select
Selects the trigger to use for starting and/or reloading the LPIT timer. This field should only be changed
when the LPIT timer channel is disabled. The TRG_SRC bit selects between internal and external trigger
signals for each channel.
The TRG_SEL bits select one trigger from the set of internal or external triggers selected by TRG_SRC.
0 Timer channel 0 trigger source is selected
1 Timer channel 1 trigger source is selected
2 Timer channel 2 trigger source is selected
. . . . . .
n Timer channel 'n' trigger source is selected
23
TRG_SRC
Trigger Source
Selects between internal or external trigger sources. The final trigger is selected by TRG_SEL depending
on which trigger source out of internal triggers or external triggers are selected by TRG_SRC.
Refer to the chip configuration section for available external trigger options. If a channel does not have an
associated external trigger then this bit for that channel should be set to 1.
0 Trigger source selected in external
1 Trigger source selected is the internal trigger
22–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18
TROT
Timer Reload On Trigger
Table continues on the next page...
Chapter 42 Low-power Periodic Interrupt Timer (LPIT)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1135