NXP Semiconductors KE1xF Series, Reference Manual, Page: 104 / 1483

6.2.12 LMEM Parity & ECC Interrupt Register (MCM_LMPEIR)
NOTE
Write 1 to the error bit in MCM_LMPEIR[23:0] can clear the
interrupt flag.
Address: E008_0000h base + 488h offset = E008_0488h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
V 0
PEELOC PE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
E1B ENC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_LMPEIR field descriptions
Field Description
31
V
Valid bit
30–29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28–24
PEELOC
Parity or ECC Error Location
• 5'h00 - a non-correctable ECC event from SRAM_L
• 5'h01 - a non-correctable ECC event from SRAM_U
• 5'h08 - a 1-bit correctable ECC event from SRAM_L
• 5'h09 - a 1-bit correctable ECC event from SRAM_U
• 5'h14 - a PC Tag Parity Error
• 5'h15 - a PC Data Parity Error
23–16
PE
Parity Error
• [21] - PC Data Parity Error
• [20] - PC Tag Parity Error
• [19] - RESERVED
• [18] - RESERVED
15–8
E1B
E1Bn = ECC 1-bit Error n
• PEIR[15:10] - Reserved
• PEIR[9] - 1-bit Error detected on SRAM_U
• PEIR[8] - 1-bit Error detected on SRAM_L
ENC ENCn = ECC Noncorrectable Error n
Table continues on the next page...
Memory map/register descriptions
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
104 NXP Semiconductors