NXP Semiconductors KE1xF Series, Reference Manual, Page: 1020 / 1483

FTMx_PWMLOAD field descriptions (continued)
Field Description
0
CH0SEL
Channel 0 Select
0 Channel match is not included as a reload opportunity.
1 Channel match is included as a reload opportunity.
41.4.28 Half Cycle Register (FTMx_HCR)
The Half Cycle Register contains the match value for FTM half cycle reload feature.
After FTM counter reaches this value, a reload opportunity is generated if
FTM_PWMLOAD[HCSEL] is enabled.
Writing to the HCR register latches the value into a buffer. The HCR register is updated
with the value of its write buffer according to
Registers updated from write buffers .
Address: Base a 9Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
HCVAL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_HCR field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
HCVAL Half Cycle Value
41.4.29 Mirror of Modulo Value (FTMx_MOD_MIRROR)
This register contains the integer and fractional modulo value for the FTM counter.
Address: Base a 200h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MOD FRACMOD
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map and register definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
1020 NXP Semiconductors