NXP Semiconductors KE17Z Series, User Manual, Page: 11 / 37

Main Clock
Divider value:
1 - 256
1 clock cycle
t1 t2 t3
Divider Main Clock before
going to SSC logic
SSC output
Figure 10. Timing of the advance clock generation with SSC enabled
As shown in Figure 10 , t1 and t2 determine the SSC output 1's period and t3 determines the SSC output 0's period.
Equation 2 shows the advanced clock generation, with SSC enabled when TSIx_SSC0[SSC_MODE] = 00/01b.
Switcℎing Clock =
Main Clock
SSC_PRESCALE_NUM + 1 × t1 + t2 + t3
Equation 2.
• When TSIx_SSC0[SSC_MODE] = 00b, t2 can be random (PRBS).
• When TSIx_SSC0[SSC_MODE] = 01b, t2 can be the range of TSIx_SSC2[MOVE_NOCHARGE_MIN] to
TSIx_SSC2[MOVE_NOCHARGE_MAX].
The generation of switching clock includes:
• The switching clock can be generated as a pseudo random clock using the Pseudo-Random Binary Sequence (PRBS)
method by setting TSI_SSC0[SSC_MODE] = 00. t2 is configured as the random width.
Table 6. TSI_SSC0[SSC_MODE] = 00, PRBS mode
Variable Register Clock cycle Description
t1 TSIx_SSC0[BASE_NOCHARGE_NUM] 1 - 16 SSCHighWidth
t2 TSIx_SSC0[PRBS_OUTSEL] 2 - 15 SSCHighRandomWidth
t3 TSIx_SSC0[CHARGE_NUM] 1 - 16 SSCLowWidth
• Switching Clock can be generated in a configurable up-down counter method by setting TSI_SSC0[SSC_MODE] = 01. The
range of t2 is limited by TSI_SSC2[MOVE_NOCHARGE_MIN] and TSI_SSC2[MOVE_NOCHARGE_MAX].
Table 7. TSI_SSC0[SSC_MODE] = 01, up-down counter mode
Variable Register Clock cycle Description
t1 TSI_SSC0[BASE_NOCHARGE_NUM] 1 - 16 SSCHighWidth
t2 TSI_SSC2[MOVE_NOCHARGE_MIN]
TSI_SSC2[MOVE_NOCHARGE_MAX] MAX-MIN SSCHighCounterWidth
Table continues on the next page...
NXP Semiconductors
TSI self-cap mode introduction
KE17Z Dual TSI User Guide, Rev. 0, 05 May 2022
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