NXP Semiconductors K32 L2A Series, Reference Manual, Page: 967 / 1379

PCC Register
36.2.2.8.2 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PR
CGC
INUS
E
Reserved PCS Reserved
W
Reset
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Rese
rved
Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
36.2.2.8.3 Fields
Field Function
31
PR
This bit shows whether the peripheral is present on this device.
0 - disabled
1 - enabled
30
CGC
This read/write bit enables the clock gate for the peripheral.
0 - Clock disabled
1 - Clock enabled
29
INUSE
This read-only bit indicates the peripheral is being used.
0 - Peripheral is not being used.
1 - Peripheral is being used.
28-27
—
This read-only bit field is reserved and always has the value 0.
26-24
PCS
This read/write bit field is used for peripherals that support various clock selections. At SOC integration,
each peripheral is assigned either the 'slow' clock source choices or the 'fast' clock source choices.
This field can only be written when the CGC bit is 0 (clock disabled). Likewise, if the INUSE flag is set,
this field is locked.
000 - Clock is off (or test clock is enabled).
001 - OSCCLK - System Oscillator Bus Clock.
010 - SCGIRCLK - Slow IRC Clock.
011 - SCGFIRCLK - Fast IRC Clock.
100 - Reserved.
101 - Reserved.
110 - SCGPCLK System PLL clock .
Table continues on the next page...
Chapter 36 Peripheral Clock Control (PCC)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 967