NXP Semiconductors K32 L2A Series, Reference Manual, Page: 886 / 1379

34.4.10 Processor 0 Count Register (MSCM_CP0COUNT)
The register provides a CPU-specific response indicating the total number of processor
cores in the chip configuration.
Address: 4000_1000h base + 2Ch offset = 4000_102Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 PCNT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 * *
* Notes:
PCNT field: See bit field description •
MSCM_CP0COUNT field descriptions
Field Description
31–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
PCNT Processor Count
This read-only field defines the processor count for the chip configuration:
PCNT = 00
34.4.11 Processor 0 Configuration Register (MSCM_CP0CFGn)
The register provides information on the Level 1 caches (if present).
Address: 4000_1000h base + 30h (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ICSZ ICWY DCSZ DCWY
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MSCM Memory Map/Register Definition
K32 L2A Reference Manual, Rev. 2, 01/2020
886 NXP Semiconductors