NXP Semiconductors K32 L2A Series, Reference Manual, Page: 878 / 1379

34.4 MSCM Memory Map/Register Definition
34.4.1 CPU Configuration Memory Map and Registers
The CPU configuration portion of the MSCM module provides a set of memory-mapped
read-only addresses defining the processor set-up. This portion of the MSCM
programming model can only be accessed with privileged mode 32-bit read references;
any other access type or size are terminated with an error. If the processor is logically not
included in the chip configuration, then reads of its configuration registers return zeroes.
The CPU Configuration registers are organized based on the logical processor number
(not any type of physical port number) and partitioned into 3 equal sections:
Table 34-1. CPU Configuration Register Sections
Offset addresses Function
0x000 - 0x01F Defines the generic processor "x" configuration. This region is only accessible to the processor core;
reads by non-core bus masters are treated as read-as-zero (RAZ) accesses.
0x020 - 0x03F Defines the configuration information for processor 0 (CP0). This region is accessible to any bus
master.
0x040 - 0x05F Reserved; reads of this section are read as zero (RAZ).
Reads from any other bus master return all zeroes. Attempted user mode or write
accesses are terminated with an error.
MSCM memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_1000 Processor X Type Register (MSCM_CPxTYPE) 32 R See section 34.4.2/879
4000_1004 Processor X Number Register (MSCM_CPxNUM) 32 R See section 34.4.3/880
4000_1008 Processor X Master Register (MSCM_CPxMASTER) 32 R See section 34.4.4/881
4000_100C Processor X Count Register (MSCM_CPxCOUNT) 32 R See section 34.4.5/882
4000_1010 Processor X Configuration Register (MSCM_CPxCFG0) 32 R See section 34.4.6/882
4000_1014 Processor X Configuration Register (MSCM_CPxCFG1) 32 R See section 34.4.6/882
4000_1018 Processor X Configuration Register (MSCM_CPxCFG2) 32 R See section 34.4.6/882
4000_101C Processor X Configuration Register (MSCM_CPxCFG3) 32 R See section 34.4.6/882
4000_1020 Processor 0 Type Register (MSCM_CP0TYPE) 32 R See section 34.4.7/883
4000_1024 Processor 0 Number Register (MSCM_CP0NUM) 32 R See section 34.4.8/884
4000_1028 Processor 0 Master Register (MSCM_CP0MASTER) 32 R See section 34.4.9/885
Table continues on the next page...
MSCM Memory Map/Register Definition
K32 L2A Reference Manual, Rev. 2, 01/2020
878 NXP Semiconductors