NXP Semiconductors K32 L2A Series, Reference Manual, Page: 871 / 1379

33.2.2 Crossbar Switch (AXBS) Master Configuration
(MCMx_PLAMC)
PLAMC is a 16-bit read-only register identifying the presence/absence of bus master
connections to the device's crossbar switch. For MCM0_PLAMC, the reset value is
0x000F. For MCM1_PLAMC, the reset value is 0x0007.
Address: F000_3008h base + Ah offset = F000_3012h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 AMC
Write
Reset 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
MCMx_PLAMC field descriptions
Field Description
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input
port.
0 A bus master connection to AXBS input port n is absent
1 A bus master connection to AXBS input port n is present
33.2.3 Platform Control Register (MCMx_PLACR)
The PLACR register selects the arbitration policy for the crossbar masters and configures
the flash memory controller.
The speculation buffer and cache in the flash memory controller is configurable via
PLACR[15:10].
The speculation buffer is enabled only for instructions after reset. It is possible to have
these states for the speculation buffer:
DFCS EFDS Description
0 0 Speculation buffer is on for instruction
and off for data.
0 1 Speculation buffer is on for instruction
and on for data.
1 X Speculation buffer is off.
Chapter 33 Miscellaneous Control Module (MCM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 871