NXP Semiconductors K32 L2A Series, Reference Manual, Page: 852 / 1379

• "Fast Start" configuration minimizes the memory-mapped register write
overhead
• Supports two methods to determine when result is valid, including software
polling
• Configurable divide-by-zero response
• Pipelined design processes 2 bits per cycle with early termination exit for minimum
execution time
32.1.2 Block diagram
A generic block diagram of the processor core and platform for this class of ultra low-end
microcontrollers is shown in
Figure 32-1 . The MMDVSQ module’s location as a
memory-mapped co-processor is highlighted.
AXBS
CM0+ Core Platform
FMC
LD/ST
Dbg
Cortex-M0+ Core
AHB Bus
AGU
RAM
Array
32
Dec
SHFT
ALU
DMA_4ch
NVM
Array
PRAM
32
GPIO
PBRIDGE
BME
32
IO Port
Slave
Peripherals
Alt-Master
-Lite
m0
s1
s2
s0
m3
m2
NVIC
Fetch
Rn
MUL
MTB Port
MTB
MCM
MMDVSQ
Figure 32-1. Generic Cortex-M0+ Core Platform Block Diagram
Next, a block diagram of the internal structure of the MMDVSQ module is presented. See
Figure 32-2 .
Introduction
K32 L2A Reference Manual, Rev. 2, 01/2020
852 NXP Semiconductors