NXP Semiconductors K32 L2A Series, Reference Manual, Page: 846 / 1379

receiver synchronizes its bit times to this start bit time. For the rest of the character
reception, the infrared decoder's counter and the receiver's bit time counter count
independently from each other.
31.3.3.4.2 Noise filtering
Any further rising edges detected during the first half of the infrared decoder counter are
ignored by the decoder. Any pulses less than one oversampling baud clock can be
undetected by it regardless of whether it is seen in the first or second half of the count.
31.3.3.4.3 Low-bit detection
During the second half of the decoder count, a rising edge is decoded as a 0, which is sent
to the receiver. The decoder counter is also reset.
31.3.3.4.4 High-bit detection
At OSR oversampling baud rate clocks after the previous rising edge, if a rising edge is
not seen, then the decoder sends a 1 to the receiver.
If the next bit is a 0, which arrives late, then a low-bit is detected according to Low-bit
detection . The value sent to the receiver is changed from 1 to a 0. Then, if a noise pulse
occurs outside the receiver's bit time sampling period, then the delay of a 0 is not
recorded as noise.
31.3.4 Additional LPUART functions
The following sections describe additional LPUART functions.
31.3.4.1 8-bit, 9-bit and 10-bit data modes
The LPUART transmitter and receiver can be configured to operate in 9-bit data mode by
setting the LPUART_CTRL[M] or 10-bit data mode by setting LPUART_CTRL[M10].
In 9-bit mode, there is a ninth data bit in 10-bit mode there is a tenth data bit. For the
transmit data buffer, these bits are stored in LPUART_CTRL[T8] and
LPUART_CTRL[T9]. For the receiver, these bits are held in LPUART_CTRL[R8] and
LPUART_CTRL[R9]. They are also accessible via 16-bit or 32-bit accesses to the
LPUART_DATA register.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
846 NXP Semiconductors