NXP Semiconductors K32 L2A Series, Reference Manual, Page: 835 / 1379

31.2.12 LPUART Watermark Register (LPUARTx_WATER)
This register provides the ability to set a programmable threshold for notification of
needing additional transmit data. This register may be read at any time but must be
written only when CTRL[TE] is not set.
Address: Base a 2Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RXCOUNT
RXWATER
TXCOUNT
TXWATER
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPUARTx_WATER field descriptions
Field Description
31–24
RXCOUNT
Receive Counter
The value in this register indicates the number of datawords that are in the receive FIFO/buffer. If a
dataword is being received, that is, in the receive shift register, it is not included in the count. This value
may be used in conjunction with FIFO[RXFIFOSIZE] to calculate how much room is left in the receive
FIFO/buffer.
23–16
RXWATER
Receive Watermark
When the number of datawords in the receive FIFO/buffer is greater than the value in this register field, an
interrupt or a DMA request is generated. For proper operation, the value in RXWATER must be set to be
less than the receive FIFO/buffer size as indicated by FIFO[RXFIFOSIZE] and FIFO[RXFE] and must be
greater than 0.
15–8
TXCOUNT
Transmit Counter
The value in this register indicates the number of datawords that are in the transmit FIFO/buffer. If a
dataword is being transmitted, that is, in the transmit shift register, it is not included in the count. This
value may be used in conjunction with FIFO[TXFIFOSIZE] to calculate how much room is left in the
transmit FIFO/buffer.
TXWATER Transmit Watermark
When the number of datawords in the transmit FIFO/buffer is equal to or less than the value in this register
field, an interrupt or a DMA request is generated. For proper operation, the value in TXWATER must be
set to be less than the size of the transmit buffer/FIFO size as indicated by FIFO[TXFIFOSIZE] and
FIFO[TXFE].
31.3 Functional description
The LPUART supports full-duplex, asynchronous, NRZ serial communication and
comprises a baud rate generator, transmitter, and receiver block. The transmitter and
receiver operate independently, although they use the same baud rate generator. The
following describes each of the blocks of the LPUART.
Chapter 31 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 835