NXP Semiconductors K32 L2A Series, Reference Manual, Page: 797 / 1379

30.3 Memory map and register definition
NOTE
The LPTMR registers are reset only on a POR or LVD event.
See
LPTMR power and reset for more details.
LPTMR memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_4000 Low Power Timer Control Status Register (LPTMR0_CSR) 32 R/W 0000_0000h 30.3.1/797
4003_4004 Low Power Timer Prescale Register (LPTMR0_PSR) 32 R/W 0000_0000h 30.3.2/799
4003_4008 Low Power Timer Compare Register (LPTMR0_CMR) 32 R/W 0000_0000h 30.3.3/800
4003_400C Low Power Timer Counter Register (LPTMR0_CNR) 32 R/W 0000_0000h 30.3.4/801
400B_5000 Low Power Timer Control Status Register (LPTMR1_CSR) 32 R/W 0000_0000h 30.3.1/797
400B_5004 Low Power Timer Prescale Register (LPTMR1_PSR) 32 R/W 0000_0000h 30.3.2/799
400B_5008 Low Power Timer Compare Register (LPTMR1_CMR) 32 R/W 0000_0000h 30.3.3/800
400B_500C Low Power Timer Counter Register (LPTMR1_CNR) 32 R/W 0000_0000h 30.3.4/801
30.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)
Address: Base a 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TDRE
TCF
TIE TPS TPP TFC TMS TEN
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPTMRx_CSR field descriptions
Field Description
31–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
TDRE
Timer DMA Request Enable
When TDRE is set, the LPTMR DMA Request is generated whenever TCF is also set and the TCF is
cleared when the DMA Controller is done.
Table continues on the next page...
Chapter 30 Low-Power Timer (LPTMR)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 797